AXI Manager over PCIe Example
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Hello,
I am trying to understand how to set up the MathWorks PCIe AXI Manager IP for Xilinx FPGAs. I read all related articles in the MathWorks website and I was able to create a Vivado project and add the IP to this project using the function "setupAXIManagerForVivado" in Matlab. I was looking at the example provided in the following article that uses a KCU116 Evaluation Kit:
However, I am not able to find the example anywhere. I tried to create it following the instructions provided in the article, but there is a file that does not exist "pcieAXIMcreateproject.tcl". I thought this was part of the HDL coder and verifier support packages, but I could not find it in my local installation, so I just want to know if this example is available anywhere as I want to undrerstand better how to set up this IP.
I am using Vivado 2022.1 and Matlab R2023b
Thank you,
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