SystemC code generation directly from SIMULINK model
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I have a SIMULINK model designs that have been compiled as generic ASIC HDL. I would like to convert the design to a SystemC model to start presilicon software development.
The references to SystemC generation that I found so far all assumes starting from MATLAB not Simulink https://www.mathworks.com/help/hdlcoder/systemc-code-generation-from-matlab.html Another question posted asked if SystemC can be generated from HDL Verifier. There was no detail on the process except that SIMULINK coder is required. https://www.mathworks.com/matlabcentral/answers/120830-systemc-code-generation-from-the-hdl-verifier?s_tid=sug_su
I would like to know the steps to generated a SystemC modele from an existing Simulink design that has been successful compiled using HDL Coder.
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Kiran Kintali
2023년 12월 24일
HDL Coder generates Synthesizable VHDL, Verilog and SystemVerilog for a DUT in Simulink model for targeting ASIC/FPGA/SoC workflows.
Currently Synthesizable SystemC / C++ Code Generation for High Level Synthesis (HLS) workflows is only limited to MATLAB workflows. Simulink support is on the future roadmap. Please reach out to tech support with your usecases for Simulink support.
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Bhanu
2023년 12월 27일
Hi John,
Using HDL Verifier, you can generate SystemC TLM 2.0 models from Simulink model.
Please find examples below
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