CCSDS TM HDL Receiver implemenation in Zed board.

I am trying out CCSDS TM HDL Receiver example using Zed Board, But I am not sure how to implement that on board, (correct me if I am wrong) ,I tried IP core generation using AXI4 stream but while running on Hardware I am not able to capture the exact data, Valid and Data signal remain zero throughout. I know Data out is boolean but I am pretty sure I am not capturing actual data.

I am totally new to this concept, I was refering some documents out there and trying the best, That increased my curiosity, now I want to know more about this example and the guidance for proper implementation.

These are some of the documents I referred,

CCSDS TM HDL Receiver Example

Model Design for AXI4-Stream Interface Generation

I have also checked these Documents to get an answer,

HDL Code Generation and FPGA Synthesis from Simulink Model

Basic HDL Code Generation and FPGA Synthesis from MATLAB

Hope I will get answer soon,

Thanks In Advance

[Kranti Balaga]

Hi Vishnu,

If you want to understand the CCSDS TM receiver, the HDL example would give better understanding of HDL implemetation side of things. To understand behavioural modelling and standard protocols, follow this example

End-to-End CCSDS Telemetry Synchronization and Channel Coding Simulation with RF Impairments and Corrections - MATLAB & Simulink - MathWorks India

To deploy on the HW, the refered document will help, however, you can follow the similar example to understand the workflow from the HDL models to deploy on to the HW.

HW/SW Co-Design QPSK Transmit and Receive Using Analog Devices AD9361/AD9364 - MATLAB & Simulink Example - MathWorks India

Thanks

Kranti