HDL FIFO Reset Problem

조회 수: 9 (최근 30일)
Juan Martin de las mulas
Juan Martin de las mulas 2023년 12월 1일
댓글: Juan Martin de las mulas 2023년 12월 11일
Hi,
I'm working with HDL FIFO Classic Module and I've discovered that when I do a reset (to local reset port) , FIFO Number of register entries turns to 1 and the empty signal turns to low level. Are there anything wrong with Classic HDL FIFO module or am I missing something?
NOTE: And HDL code generated does just the descrived above
fifo_sample_count_next <= to_unsigned(16#0001#, 16) WHEN rst /= '0' ELSE
fifo_sample_count + to_unsigned(16#0001#, 16) WHEN (fifo_write_enable AND ( NOT fifo_read_enable)) = '1' ELSE
fifo_sample_count + to_unsigned(16#FFFF#, 16) WHEN (( NOT fifo_write_enable) AND fifo_read_enable) = '1' ELSE
fifo_sample_count;

답변 (1개)

Kiran Kintali
Kiran Kintali 2023년 12월 1일
Would you be able to share your sample model? You can prune it to just show HDL FIFO block.
Found a relevant report here. Need to investigate further if the issue is identical.
An update patch is planned for this bug.
  댓글 수: 6
Kiran Kintali
Kiran Kintali 2023년 12월 6일
The issue is resolved in the latest releases of MATLAB and HDL Coder and is being backported to previous releases. https://www.mathworks.com/support/bugreports/2982578
Do not hesitate to reach out to tech support for the update release information.
Juan Martin de las mulas
Juan Martin de las mulas 2023년 12월 11일
Hi Kiran. I'm using Matlab 2022 version. I wasn't asserting reset and pop at the same time, only set reset, but in any case... thanks!

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