Is the counter here working properly?
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I am trying to simulate a system in Simulink as shown below. It's kindof like a sigma-delta modulator. The two switches act like comparators - when the error exceeds the upper limit, +d becomes 1, otherwise it remains 0; when the error exceeds the lower limit, -d becomes 1, otherwise it remains 0. Both counters are set to count up, when there's rising edge from +d/-d.
![](https://www.mathworks.com/matlabcentral/answers/uploaded_files/1556989/image.png)
Now the system is not working as I expected, and I noticed some weired behaviour of the counter at the top: +d only has one rising edge but the counter starts to count even before the rising edge. Is the counter working properly, or I'm doing something wrong? I've also attached the simulink model if it helps.
![](https://www.mathworks.com/matlabcentral/answers/uploaded_files/1556994/image.png)
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madhan ravi
2023년 11월 30일
Have a look at Triggered and Enabled subsystem, when you respond just post the output signal scope that you would like to achieve for the specified inputs.
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