Simulink port annotations do not appear with HDL definition of wire/reg
조회 수: 3 (최근 30일)
I've been using Simulink's annotation feature to comment on various elements in my system. For instance, double click background of diagram, start typing, get an annotation. Then drag from the edge of the annotation to an element in the diagram and a line will connect the two.
These annotations appear in the generated HDL (Verilog in my case), which is great, except for one thing: they don't appear where the annotated element is defined in the HDL.
For some elements, they do. For instance, I annotated an OR gate with a long paragraph explaining why it was necessary. This appears in full right above the "assign OR_out = ..." statement in the Verilog code. This is absolutely great!
However, if I annotate an inport or outport, the annotation does not appear with the signal definition in Verilog. Instead, we have the list of module inputs and outputs, then all the signals inside the subsystem, then finally we get to a list of comments - all the annotations I made in the subsystem that were not connected to a block of some kind.
There's tremendous value in having the comments next to what they're commenting (!!!). I'm handing off the HDL to an FPGA engineer, and if I can put the kind of comments he needs right in the Simulink diagram, this is a huge help. Also, for generic annotation blocks not attached to anything, perhaps a special HDL-specific flag is possible that would identify the annotation as the "title" of the subsystem - then the annotation would go to the right place in the HDL (top of the file?).
Kiran Kintali 2023년 5월 19일
I have reported the issue to the development team.
As a workaround consider right-cliking on the port, choose port properties and use the Description: text box to enter the comment. It does seem to end up in the right place above the input port in the module/entity declaration.