how to build a chain of a custom VHDL code

Hi,

let's say I have a custom, hand-written VHDL code named "buffer.vhd", that have one boolean input and one boolean output.

I'd like to build with HDL coder, a wrapper code named "chain_of_buffer.vhd", that have one boolean input and one boolean output, and that contains n instances of "buffer.vhd" block, connected in series with each other. An additional port should be present to select the number of instances of the subsystem.

What is the most efficient way to do it?

I tried to understand examples about blackbox and for each subsystem but they are too much complicated for me.

I'm trying to bypass the issue discussed here https://it.mathworks.com/matlabcentral/answers/1916230-generating-asynchronous-delays-with-hdl-coder-in-simulink and realize a model of an asynchronous logic for third party simulator testbenches.

Thank you

Answer 1

[Vanshika Vaishnav]

Here are some guidance for required model,refer the below mentioned documentations:-

HDL Block Properties: General - MATLAB & Simulink - MathWorks India

Hierarchical Designs and Synchronous Hardware Behavior - MATLAB & Simulink - MathWorks India