pulse gate in thyristor

in fullwave fully controlled r load rectifier i cant balance the 2 pulse gate that cause wrong waveform for the thyristors

Answer 1

[Joel Van Sickel]

If you post a screenshot of your simulink model (or share the model) it might be easier to point out what the specific issue is. Here are some examples of thyrsitor based recitifiers that you can start with:

https://www.mathworks.com/help/physmod/sps/ug/thyristor-rectifiers.html

Regards,

Joel