How to generate verilog code for thisbelow function using HDL coder?

I want to know ,how to generate the verilog code for the below function(divide) using hdl coder.?

T = numerictype('Signed', false,...
    'WordLength', 80,...
    'FractionLength', 83);
a = fi(20);
b = fi(2);
c = divide(T, a, b);

Thank you.

Answer 1

[Bharath Venkataraman]

You can use the real divide hdl optimized block. Other options include the reciprocal block followed by a multiply or the divide block in Simulink.