Tri-state buffer in simulink

Hi,

I am trying to use a tri-state buffer (logic : 1,0,Z) in a simulink model in order to test a vhdl component. Any suggestions ?

I thank you in advance,

Best regards,

Answer 1

[Tim McBrayer]

Support for enumerated types was added to HDL Coder in R2014a. You could try making an enumerated type in Simulink that contained the values you need. But, I don't expect that VHDL will equate your custom enumerated type with std_logic or std_ulogic.

Answer 2

[Girish Venkataramani]

Unfortunately, there's not a concept of an inout port in Simulink and this makes it hard to model a tri-state buffer. But, we have a somewhat manual workaround:

You can set a DUT input port as a Bi-directional port in the HDL block properties for the port object (right-click on an input port, select bidirectional port type in the HDL Block properties dialog). This will generate HDL with an 'inout' type for this port.

You should then connect this port to a subsystem, which you should black-box (again, HDL block properties for Subsystem and choose 'BlackBox' for the architecture). This will give you HDL with inout port and a place-holder module (the black-boxed subsystem) connected to the inout port - you will then have to hand-code the tri-state logic in this place-holder module.

Hope this makes sense.

Answer 3

[Sergio Luis Martínez]

Una propuesta simple: Compuerta activada con 1.