Error selecting target in R2020a and Vivado 2020

조회 수: 2 (최근 30일)
Miquel Diego
Miquel Diego . 2022년 3월 22일
편집: Stefanie Schwarz . 2022년 9월 16일
Dear Community,
I am trying to get familirized with HDL generation from Simulink.
I tried the "workflow advisor" button from upper left corner.
At first stage I tried to select a board, but I got an error, see picture attached.
error: Target platform "XUP Atlys Spartan-6 development board" requires one of the following synthesis tools: Xilinx ISE
I set the HDL tool path using:
('ToolName','Xilinx Vivado','ToolPath','C:/Xilinx/Vivado/2020.1/bin')
I restarted Matlab
it did not helped..
Why is asking for a tool almost 10 years old??
What to do to get rid of the error??
Please help

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Wang Chen
Wang Chen 2022년 3월 22일
편집: Wang Chen 님. 2022년 3월 23일
Hi Miquel,
For Spartan-6 FPGA device, Xilinx requires Xilinx ISE as synthesis tool. You cannot use Xilinx Vivado for Spartan-6 device.
For newer Vivado-based FPGA device like Zynq, Zynq Ultrascale+, Kintex-7, Virtex-7, please use the IP core generation workflow in HDL Workflow Advisor. You can refer to following example to get started:
  댓글 수: 2
Wang Chen
Wang Chen 2022년 3월 23일
Hi Miquel,
Virtex-6 is also the older device that is only supported by Xilinx ISE.
Vivado only support Virtex-7 and up. This is the limitation of Xilinx tools.
I highly recommend you use IP core generation workflow for the newer Vivado-based Xilinx devices.
If you want to use the older board (Spartan-6, Virtex-6), please use Xilinx ISE as synthesis tool.

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Miquel Diego
Miquel Diego 2022년 3월 23일
Apparenlty there are two methods to work with FPGA boards and Matlab: "FPGA in the loop (FIL)" and " Turnkey".
I finally found out that >>filWizard provides a list of boards. Most of them are enabled for FIL . So I will go wiht Digilent Arty A7 and FIL




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