How to add a custom parameter in the generated module with HDL Coder,simulink?

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Hi,
I want to design an uart_tx module, which has two parameters clk_frequency and Baud_rate.
In verilog, the correct code is as below:
module uart_tx
#(
parameter CLK_FRE = 50, //clock frequency(Mhz)
parameter BAUD_RATE = 115200 //serial baud rate
)
So, which block can generate it? Thanks.

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Kiran Kintali
Kiran Kintali 2022년 3월 17일

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