How to add a custom parameter in the generated module with HDL Coder,simulink?
조회 수: 1 (최근 30일)
이전 댓글 표시
Hi,
I want to design an uart_tx module, which has two parameters clk_frequency and Baud_rate.
In verilog, the correct code is as below:
module uart_tx
#(
parameter CLK_FRE = 50, //clock frequency(Mhz)
parameter BAUD_RATE = 115200 //serial baud rate
)
So, which block can generate it? Thanks.
댓글 수: 0
채택된 답변
추가 답변 (0개)
참고 항목
Community Treasure Hunt
Find the treasures in MATLAB Central and discover how the community can help you!
Start Hunting!