Why do I receive "Unable to match the starting point because it has been elaborated in Altera or it is inside a Stateflow or an MATLAB Function block."?

When I use HDL Workflow Advisor - target workflow "Generic ASIC/FPGA", the last step 4.3. gave me a message "Failed Unable to match the starting point because it has been elaborated in Altera or it is inside a Stateflow or an MATLAB Function block.". All previous step are green. I can't understand, where is I can assign a "starting point"?

Answer 1

[Tim McBrayer]

HDL Coder is trying to backannotate the place and route timing results from Altera back onto your Simulink diagram. Due to naming changes that have occurred during Altera's synthesis process, HDL Coder cannot match up the timing information that Altera provides with the original source code. Some possible reasons as to why HDL Coder cannot successfully map the synthesis results back to the Simulink signals are given in the error message.

There is no issue with your code; this is simply a failure to backannotate the synthesis timing results.

[Kristina]

I don't know what I did, but now I receive a message "Unable to match the end point because..." etc. So, what I can try to do to fix this problem?

[Tim McBrayer]

The end point as analogous to the starting point, and has the same rationale and explanation. It's still a failure to map the data returned from Altera back to the original Simulink model.