How to convert Simulink project into Verilog or VHDL coding?

Hi all,

I have a complete project where I use MATLAB coding in S-function Level 2 as well as Simulink blocks.

I would like to convert the above project into Verilog or VHDL (I can choose but I don't know which one is better for the moment) to be implemented on a hardware FPGA design on DE0 Nano Development board.

I read in this link that (<http://uk.mathworks.com/matlabcentral/answers/15963-conversion-of-matlab-m-coding-into-verilog-hdl>) it is possible to do so by coding either in Embedded MATLAB code or on Simulink

My question is, how could I get started in order to convert the complete project to Verilog or VHDL? Could you provide some links or resources?

Also I found this link (<http://uk.mathworks.com/products/?s_cid=global_nav>) so it means it is possible to generate a HDL code using Simulink HDL Coder, but I could not find the details. Only the HDL but not Verilog?

Finally, actually I am confused, if the conversion of Simulink to VHDL/Verilog coding could be done, does it mean we do not need to use other software such as Quartus/Nios2? Forgive me if this really sounds stupid.

Forgive me as I am really new to VHDL and Verilog as well as FPGA design.

Hopefully someone could give me some inputs at least to get start. Thank you in advance.

Answer 1

[Tim McBrayer]

HDL Coder will allow you to generate either VHDL or Verilog HDL code from either MATLAB code or a Simulink design. The product page is the best place to start to begin understanding the capabilities of HDL Coder. It generates platform independent, bit-true and cycle-accurate HDL code from the input design.

HDL Coder is a code generator, and is not a HDL simulator or a FPGA synthesis tool. Any HDL simulation or synthesis requires an appropriate 3rd party EDA tool. HDL Coder does provide workflow integration with these tools. With the HDL Verifier product you can co-simulate your generated HDL code (using ModelSim or Incisive) inside the rest of your Simulink model. HDL Verifier also supports Simulink FPGA-in-loop simulation capabilities.

[want2know]

Thanks for your reply, I started looking at the demo video, hopefully I could find something to get started...

One thing puzzles me is that I don't understand why I am still asked to program ALL my codes in VHDL/Verilog if it can't be done automatically by Matlab. ( previously, I have all S-functions programmed in Matlab/Simulink , now I need to repeat the programming process again, didn't it sound time wasting? Or did I miss some important points???)

[Tim McBrayer]

If I understand you correctly, you have created one or more custom blocks using S-functions. You wish to convert these to HDL, along with native Simulink blocks, together in a larger design. And, you are wondering why you need to supply a black box HDL implementation for your custom blocks.

If this is the question you are asking, then the answer is that HDL Coder has no way to determine the behavior of the content of your S-function. HDL Coder does not have the ability to synthesize HDL from your C/C++ S-function source code; its inputs are MATLAB code and SImulink models. The only input that HDL Coder has available in this case is the Simulink simulation behavior. And, it's trivially easy to construct block behavior that cannot be determined simply by looking at the Simulink simulation's pattern of inputs and outputs of your block.