To read .mdl file into VHDL using system generator

I am working on SDR kit SMT8246, a product of Sundance. I am trying to simulink model file into VHDL using system generator. I have been following a guide which is actually very hard to follow... too much of matter...not in simple terms.. Can anyone plz explain me how to do? what blocks should I have in simulink to be loaded into Xilinx VHDL? What VHDL code should I write to make it happen?.. Plz give me some good examples...Possibly links to codes... as soon as possible plz... Thank u ...

[Kaustubha Govind]

Since you are using Xilinx System Generator, you may have better luck on Xilinx support forums.