HDL Coder and LEC tools

Hi, I've built a design in Simulink and generated HDL code from the design using the HDL coder. My problem is that the generated code does not verify correctly when I run the HDL code through Logical Equivalence Checking tools. (Formality, Formalpro, and Conformal) Are there any special considerations that I need to take on the side of Matlab/Simulink for the HDL coder to generate readable code?

[Steve Levy]

We also have problems in this area. Are there guidance information for 'math' functions generated by HDL coder?

Answer 1

[Kiran Kintali]

Can you please contact technical support with specific issues? HDLCoder generates synthesizable HDL code (VHDL and Verilog) from Simulink models and MATLAB code.

HDLCoder generates readable and traceable code and we are not aware of any issues reported w.r.to supporting the tools.

Would you be able to provide specific models and the specifics about errors in the generated code? This will help us debug the issues.

Please contact technical support for further support on this issue.

Thanks.