Using HDL Coder IP core in Xilinx Vivado instead of EDK
조회 수: 1(최근 30일)
I need to use an IP core generated with HDL Coder in Xilinx Vivado 2014.2. The core generated by the coder is intended to be used in Xilinx EDK. The IP core converter implemented in Vivado 2014.2 has troubles to identify the AXI interfaces in my core correctly, so I would have to set the AXI parameters manually, which is a very time consuming task, especially if performed more than once. Will you support direct generation of IP cores for Vivado in the future?
Wang Chen 2014년 7월 14일
Yes, the IP core generation feature for Xilinx Vivado will be supported in MATLAB R2014b release. You can already try out this feature in R2014b pre-release.