HDL Coder generates 'real' types - how to prevent that

Hello,

I am generating a large system into VHDL code using the HDL Coder. A lot of the signal types are inherited or allows Matlab to choose the best type. However, when I generate the VHDL code it uses 'real' types in certain places which is not compilable except for simulation purposes.

How do I get Simulink HDL coder to not use real types and default to say double or int32.

Answer 1

[Tim McBrayer]

There is no way to specify the default data type for Simulink to be anything except 'double'. HDL Coder will generate HDL for your model as it exists.

If you use 'single' or 'double' data types in Simulink, these will be mapped to the 'real' type in VHDL, as you have seen. If you do not wish for real typed signals to appear in your VHDL code you will need to modify your Simulink design to not contain floating point types. You can use the Simulink Fixed-Point Advisor to guide you in your choice of fixed-point types if need be.

In general, if you place Data Type Conversion blocks on your real-valued data inputs before they enter the HDL part of your design, the data type propagation will assign most Simulink signals non-double types.

Answer 2

[Siyuan XU]

Hi, You can convert all your blocks which may contain double value to have a fixed-point type output, to do so, double click on your block, at the popped up window, choose the Signal Attributes tag, then choose the Output data type as fixdt(1,16), then click Apply button. As soon as all your data type is configured, this will prevent the 'real' type from showing in your VHDL code.