generate simulink model from VHDL code?

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Roger
Roger 2014년 3월 5일
댓글: Roger 2014년 3월 6일
Hi,
I want to know if HDL coder is capable of generating simulink model from a given VHDL code? in order to intergret exist small part of design to a larger project. That will save large amount of time for development. Thanks!

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Tim McBrayer
Tim McBrayer 2014년 3월 5일
No, there is no capability within HDL Coder to generate Simulink from HDL; the tool works exclusively in the other direction.
If you need to import VHDL into a larger design, you can use HDL Coder's Black Box feature to include handwritten HDL code into a larger set of generated HDL code. You could also use HDL Verifier to cosimulate hand-written HDL code in a Simulink design.
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Roger
Roger 2014년 3월 6일
Thank you Tim, now it's more clear to me.

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