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plotMemoryStatistics

Plot performance data obtained from AXI interconnect monitor

Description

example

plotMemoryStatistics(profiler) generates visualizations of the performance data from the AXI interconnect monitor IP running on your hardware board. The profiler object represents a connection to that IP. When the AXI interconnect monitor is configured in 'Profile' mode, this function launches a performance plot tool. You can configure the tool to plot bandwidth, burst count, and average transaction latency. In 'Trace' mode, this function opens the Logic Analyzer to view detailed memory transaction event data.

Examples

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The AXI interconnect monitor (AIM) is an IP core that collects performance metrics for an AXI-based FPGA design. Create an socIPCore object to setup and configure the AIM IP, and use the socMemoryProfiler object to retrieve and display the data.

For an example of how to configure and query the AIM IP in your design using MATLAB® as AXI Master, see Analyze Memory Bandwidth Using Traffic Generators. Specifically, review the soc_memory_traffic_generator_axi_master.m script that configures and monitors the design on the device.

The performance monitor can collect two types of data. Choose Profile mode to collect average transaction latency and counts of bytes and bursts. In this mode, you can launch a performance plot tool, and then configure the tool to plot bandwidth, burst count, and transaction latency. Choose Trace mode to collect detailed memory transaction event data and view the data as waveforms.

Mode = 'Profile'; % or 'Trace'

To obtain diagnostic performance metrics from your generated FPGA design, you must set up a JTAG connection to the device from MATLAB. Load a .mat file that contains structures derived from the board configuration parameters. This file was generated by the SoC Builder tool. These structures describe the memory interconnect and masters configuration such as buffer sizes and addresses. Use the socHardwareBoard object to set up the JTAG connection.

load('soc_memory_traffic_generator_zc706_aximaster.mat');
hwObj = socHardwareBoard('Xilinx Zynq ZC706 evaluation kit','Connect',false);
AXIMasterObj = socAXIMaster(hwObj);

Configure the AIM. The socIPCore object provides a function that performs this initialization. Then, create an socMemoryProfiler object to gather the metrics.

apmCoreObj = socIPCore(AXIMasterObj,perf_mon,'PerformanceMonitor','Mode',Mode);
initialize(apmCoreObj);
profilerObj = socMemoryProfiler(hwObj,apmCoreObj);

Retrieve performance metrics or signal data from a design running on the FPGA by using the socMemoryProfiler object functions.

For 'Profile' mode, call the collectMemoryStatistics function in a loop.

NumRuns = 100;
for n = 1:NumRuns
    collectMemoryStatistics(profilerObj);
end
JTAG design setup time is long relative to FPGA transaction times, and if you have a small number of transactions in your design, they might have already completed by the time you query the monitor. In this case, the bandwidth plot shows only one sample, and the throughput calculation is not accurate. If this situation occurs, increase the total number of transactions the design executes.

For 'Trace' mode, call the collectMemoryStatistics function once. This function stops the IP from writing transactions into the FIFO in the AXI interconnect monitor IP, although the transactions continue on the interconnect. Set the size of the transaction FIFO, Trace capture depth, in the configuration parameters of the model, under Hardware Implementation > Target hardware resources > FPGA design (debug).

collectMemoryStatistics(profilerObj);

Visualize the performance data by using the plotMemoryStatistics function. In 'Profile' mode, this function launches a performance plot tool, and you can configure the tool to plot bandwidth, burst count, and average transaction latency. In 'Trace' mode, this function opens the Logic Analyzer tool to view burst transaction event data.

plotMemoryStatistics(profilerObj);

Input Arguments

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Memory profiler object, specified as an socMemoryProfiler object that provides access to the AXI memory interconnect IP running on the hardware board.

Introduced in R2019a