sldvrun

R2026b

Run Simulink Design Verifier analysis on model

Syntax

status = sldvrun

status = sldvrun(model)

status = sldvrun(subsystem)

status = sldvrun(model,options)

status = sldvrun(subsystem,options)

[status,filenames,msg] = sldvrun(model,options)

[status,filenames,msg] = sldvrun(model,options,showUI,startCov)

Description

status = sldvrun runs Simulink^® Design Verifier™ analysis on the model using its saved configuration settings or the active configuration set. Use this to generate test cases for model coverage, identify design errors by generating counterexamples, or verify model properties.

status = sldvrun(model) analyzes the specified model using Simulink Design Verifier configuration settings saved in the model or the active configuration set.

status = sldvrun(subsystem) extracts the atomic subsystem subsystem into a temporary Simulink model and analyzes it.

status = sldvrun(model,options) analyzes model using the settings specified in the Sldv.Options object options.

status = sldvrun(subsystem,options) analyzes an atomic subsystem using the specified analysis options.

[status,filenames,msg] = sldvrun(model,options) returns filenames, the paths to all generated artifacts, and msg, any error or warning messages produced during analysis.

[status,filenames,msg] = sldvrun(model,options,showUI,startCov) controls the log window display based on showUI and provides existing coverage data based on startCov to guide analysis toward uncovered objectives.

Examples

Run Test Generation Analysis and Inspect Results

Configure Simulink® Design Verifier™ options for MCDC test generation and analyze a model. Then, inspect the results based on analysis status.

Open the sldvdemo_cruise_control model.

open_system("sldvdemo_cruise_control");

Create and configure Simulink Design Verifier analysis options.

opts = sldvoptions;
opts.Mode = "TestGeneration";
opts.ModelCoverageObjectives = "MCDC";
opts.TestSuiteOptimization = "Auto";
opts.MaxProcessTime = 7200;
opts.SaveHarnessModel = "on";
opts.SaveReport = "on";

Run the analysis and capture all outputs.

[status,files,msg] = sldvrun("sldvdemo_cruise_control",opts);

17-Aug-2026 16:31:57
Checking compatibility for test generation: model 'sldvdemo_cruise_control'
Compiling model...done
Building model representation...done

17-Aug-2026 16:32:00

'sldvdemo_cruise_control' is compatible for test generation with Simulink Design Verifier.
Generating tests...


Generating output files:

    Harness model:
    /tmp/Bdoc26b_3362262_762230/tpe5ff1471/sldv-ex67396824/sldv_output/sldvdemo_cruise_control/sldvdemo_cruise_control_harness.slx

    Report:
    /tmp/Bdoc26b_3362262_762230/tpe5ff1471/sldv-ex67396824/sldv_output/sldvdemo_cruise_control/sldvdemo_cruise_control_report.html

17-Aug-2026 16:32:27
Results generation completed.

    Data file:
    /tmp/Bdoc26b_3362262_762230/tpe5ff1471/sldv-ex67396824/sldv_output/sldvdemo_cruise_control/sldvdemo_cruise_control_sldvdata.mat

Inspect the results according to the analysis status. When the analysis status is 1, Simulink Design Verifier runs sldvruntest using the test data file and displays a summary of the generated test cases and the location of the HTML report.

if status == 1
    outData = sldvruntest("sldvdemo_cruise_control", files.DataFile);
    fprintf("Complete. %d test case(s). Report: %s\n", numel(outData), files.Report);

If the analysis status is 0, Simulink Design Verifier filters the msg structure array to identify messages of type "Error".

elseif status == 0
    errMsgs = msg(strcmp({msg.type}, "Error"));
    arrayfun(@(m) fprintf("ERROR: %s\n", m.msg), errMsgs);

If the status is -1, Simulink Design Verifier shows that the analysis exceeded the configured maximum analysis time limit.

elseif status == -1
    fprintf("Timed out (%ds).\n", opts.MaxProcessTime);
end

Complete. 4 test case(s). Report: /tmp/Bdoc26b_3362262_762230/tpe5ff1471/sldv-ex67396824/sldv_output/sldvdemo_cruise_control/sldvdemo_cruise_control_report.html

Open the analysis report to review the generated test cases.

Detect Design Errors in a Model

Configure analysis for design error detection and inspect output messages.

Open the model sldvdemo_flipflop.

open_system("sldvdemo_flipflop");

Create and configure Simulink® Design Verifier™ options for design error detection analysis.

opts = sldvoptions;
opts.Mode = "DesignErrorDetection";
opts.DetectIntegerOverflow = "on";
opts.DetectDivisionByZero = "on";
opts.DetectDeadLogic = "on";
opts.MaxProcessTime = 120;
opts.SaveReport = "on";

Run the analysis.

[status,files,msg] = sldvrun("sldvdemo_flipflop",opts);

17-Aug-2026 16:31:35
Checking compatibility for design error detection: model 'sldvdemo_flipflop'
Compiling model...done
Building model representation...done

17-Aug-2026 16:31:37

'sldvdemo_flipflop' is compatible for design error detection with Simulink Design Verifier.
Detecting design errors...


Generating output files:

    Report:
    /tmp/Bdoc26b_3362262_762230/tpe5ff1471/sldv-ex13177216/sldv_output/sldvdemo_flipflop/sldvdemo_flipflop_report.html

17-Aug-2026 16:31:52
Results generation completed.

    Data file:
    /tmp/Bdoc26b_3362262_762230/tpe5ff1471/sldv-ex13177216/sldv_output/sldvdemo_flipflop/sldvdemo_flipflop_sldvdata.mat

Inspect the results according to the analysis status. When the analysis status is 1, Simulink Design Verifier shows the path to the generated HTML report.

if status == 1
    fprintf("Error detection complete. Report: %s\n", files.Report);
    web(files.Report);

For any other status, Simulink Design Verifier shows diagnostic message with its error type.

else
    fprintf("Analysis returned status=%d.\n", status);
    for k = 1:numel(msg)
        fprintf("  [%s] %s\n", msg(k).type, msg(k).msg);
    end
end

Error detection complete. Report: /tmp/Bdoc26b_3362262_762230/tpe5ff1471/sldv-ex13177216/sldv_output/sldvdemo_flipflop/sldvdemo_flipflop_report.html

Open the report in the MATLAB® HTML Viewer and inspect the results.

Input Arguments

model — Model to analyze

character vector | string scalar | model handle

Simulink model to analyze, specified as a character vector, string scalar, or numeric model handle. The model must be loaded in the current MATLAB^® session when you invoke sldvrun.

subsystem — Atomic subsystem to analyze

character vector | string scalar | subsystem handle

Atomic subsystem to analyze, specified as a character vector, string scalar, or numeric handle representing the full path to an atomic subsystem within an open Simulink model. The subsystem must have Is Atomic check enabled in the context menu. Simulink Design Verifier extracts the subsystem into a temporary model, analyzes it, and closes the temporary model.

options — Analysis options

Sldv.Options object

Simulink Design Verifier analysis options, specified as an Sldv.Options object. The object specifies the analysis mode, coverage objectives, timeout, output file locations, and other analysis options. When omitted, Simulink Design Verifier analysis uses the saved model configuration settings.

showUI — Option to view the analysis progress in the Results Summary dialog box

false or 0 (default) | true or 1

Option to direct output to Results Summary dialog box, specified as a numeric or logical 1 (true) or 0 (false). When true, diagnostic messages are displayed in the Simulink Design Verifier log window. When false (default), messages are displayed in the MATLAB Command Window.

startCov — Existing coverage data to guide analysis

[] (default) | cvdata object

Existing coverage data to guide analysis, specified as a cvdata (Simulink Coverage) object from a prior simulation, or [] for no prior coverage. When provided, Simulink Design Verifier analyzes objectives not satisfied by the prior coverage data.

Output Arguments

status — Analysis completion status

1 | 0 | -1

Analysis completion status, returned as one of these values:

• 1— Analysis ran to completion and results were saved.

• 0— Analysis encountered an error and did not complete. Inspect msg for details.

• -1— Analysis timed out. For workarounds, see Perform Analysis on Large and Complex Models.

Data Types: double

filenames — Paths to generated artifacts

structure

Paths to generated artifacts, returned as a structure with these fields:

Field	Generated when	Description
DataFile	Always (when status == 1)	MAT file that contains the analysis results. Pass the MAT file to sldvruntest, sldvmakeharness, or sldvreport for further processing.
HarnessModel	When opts.SaveHarnessModel == "on"	Simulink harness model.
Report	When opts.SaveReport == "on"	HTML analysis report.
ExtractedModel	When analyzing a subsystem	Simulink model extracted from the subsystem.
BlockReplacementModel	When opts.BlockReplacement == "on"	Simulink model with unsupported blocks replaced by stubs.

Empty fields indicate the corresponding artifact was not generated. Check isempty(filenames.DataFile) before using the data file.

msg — Analysis status messages

structure array

Analysis status messages, returned as a structure array with these fields:

Field	Description
sourceFullName	Full hierarchical path of the model element that caused the message.
objH	Handle to the model object that caused the message. Use open_system(msg.objH) to navigate to it.
reportedBy	Name of the component that generated the message.
msg	Human-readable message text.
msgid	Message identifier (use to filter or search for known issues).
msgargs	Arguments used to construct the message text.
type	Message severity: "Error", "Warning", or "Info".

Limitations

• Continuous-time models with stiff ODE solvers (such as ode15s) may need solver reconfiguration or subsystem extraction to enable analysis. Analysis only supports fixed-step solver configuration.

• Models containing variable-size signals are not supported and cause the function to return a status of 0. Use block replacement to stub out blocks generating variable-size signals, or restructure the model. For a complete list of unsupported blocks, see Unsupported Simulink Blocks in Analysis.

• S-functions without a TLC file or without a registered block replacement rule are flagged as incompatible. Use opts.BlockReplacement == "on" with a replacement rule, or use sldvextract to isolate the analysis scope.

For more information, see Limitations of Simulink Design Verifier for Simulink Software Features.

More About

Working With Analysis Results

Use files.DataFile, which is a MAT file containing an sldvData structure. It is the primary artifact of every Simulink Design Verifier analysis results apart from the report.

d = load(files.DataFile); 

files.DataFile contains all objectives, generated test cases, model object information, and analysis metadata.

Troubleshoot and Improve Analysis Results

When analysis results are incomplete, undecided, or slower than expected, Simulink Design Verifier provides guidance on reducing model complexity, addressing unsupported features, and refining analysis configuration. For systematic troubleshooting, see Analyze and Resolve Undecided Objective Statuses.

Symptom	Root Cause	Fix
status == -1 (timeout)	Model too complex for the time budget	Raise the MaxProcessTime. Reduce MaxTestCaseSteps. Keep opts.TestSuiteOptimization == "Auto". Extend from partial files.DataFile rather than restarting.
status == 0 with unsupported construct	Variable-size signals, S-functions without TLC, stiff ODE solver, algebraic loops	Run sldvcompat for actionable diagnostics. Use opts.BlockReplacement == "on" or sldvextract to isolate scope.
filenames.HarnessModel is empty	opts.SaveHarnessModel defaults to "off"	Set opts.SaveHarnessModel == "on" before calling sldvrun, or call sldvmakeharness(model, files.DataFile) afterward.
Unexpected dead logic	Parameters fixed at a single value; over-constrained model	Set opts.ParameterConfiguration == "Auto" or define parameter ranges; verify model is not over-constrained by sldv.assume blocks.
Many Undecided objectives	Solver budget exhausted on hard objectives	Extend from partial results; reduce scope to subsystem; switch from "MCDC" to "Decision".

Tips

• Run sldvcompat before calling sldvrun for large and complex models. sldvrun on an incompatible model wastes solver time and produces less actionable errors.

• The model must be open in Simulink before calling sldvrun. An error occurs if the model is not loaded.

• Keep opts.TestSuiteOptimization set to "Auto". Other values such as "IndividualObjectives" typically decide fewer objectives in practice.

• sldvrun does not modify the original model structure or parameters. Analysis artifacts are written to the directory specified by opts.OutputDir (default: sldv_output/$ModelName$).

Alternatives

To run an analysis with Simulink Design Verifier, on the Design Verifier tab, in the Mode section, use any of these options:

• Select Design Error Detection, then click Detect Design Errors.

• Select Test Generation, then click Generate Tests.

• Select Property Proving, then click Prove Properties.

Version History

Introduced in R2007a

R2024b: Version History

The msg output argument allows retrieval of error and warning information programmatically. Simulink Design Verifier now reports structured error messages when analysis fails on an incompatible model.