Dot Product
Generate dot product of two vectors
Libraries:
Simulink /
Math Operations
HDL Coder /
Math Operations
Description
The Dot Product block generates the dot product of the input vectors. The
scalar output, y
, is equal to the MATLAB^{®} operation
y = sum(conj(u1) .* u2 )
where u1
and u2
represent the input vectors. The
inputs can be vectors, column vectors (singlecolumn matrices), or scalars. If both
inputs are vectors or column vectors, they must be the same length. If
u1
and u2
are both column vectors, the block
outputs the equivalent of the MATLAB expression u1'*u2
.
The elements of the input vectors can be real or complexvalued signals. The signal type (complex or real) of the output depends on the signal types of the inputs.
Input 1  Input 2  Output 

real 
real 
real 
real 
complex 
complex 
complex 
real 
complex 
complex 
complex 
complex 
Examples
Ports
Input
Port_1 — First operand input signal
scalar  vector
Signal representing the first operand to the dot product calculation.
Data Types: single
 double
 half
 int8
 int16
 int32
 int64
 uint8
 uint16
 uint32
 uint64
 fixed point
Port_2 — Second operand input signal
scalar  vector
Signal representing the second operand to the dot product calculation.
Data Types: single
 double
 half
 int8
 int16
 int32
 int64
 uint8
 uint16
 uint32
 uint64
 fixed point
Output
Port_1 — Dot product output signal
scalar  vector
Output signal resulting from the dot product calculation of the two input signals.
Data Types: single
 double
 half
 int8
 int16
 int32
 int64
 uint8
 uint16
 uint32
 uint64
 fixed point
Parameters
Require all inputs to have the same data type — Require all inputs to have the same data type
on
(default)  off
Clear this check box for all the inputs to have different data types.
Programmatic Use
Block Parameter:
InputSameDT 
Type: character vector 
Values: 'on'
 'off' 
Default:
'on' 
Output minimum — Minimum output value for range checking
[]
(default)  scalar
Lower value of the output range that Simulink^{®} checks.
Simulink uses the minimum to perform:
Parameter range checking (see Specify Minimum and Maximum Values for Block Parameters) for some blocks.
Simulation range checking (see Specify Signal Ranges and Enable Simulation Range Checking).
Automatic scaling of fixedpoint data types.
Optimization of the code that you generate from the model. This optimization can remove algorithmic code and affect the results of some simulation modes such as SIL or external mode. For more information, see Optimize using the specified minimum and maximum values (Embedded Coder).
Note
Output minimum does not saturate or clip the actual output signal. Use the Saturation block instead.
Programmatic Use
Block Parameter:
OutMin 
Type: character vector 
Values: '[ ]' 
scalar 
Default: '[ ]' 
Output maximum — Maximum output value for range checking
[]
(default)  scalar
Specify the upper value of the output range that Simulink checks as a finite, real, double, scalar value.
Note
If you specify a bus object as the data type for this block, do not set the
maximum value for bus data on the block. Simulink ignores this setting. Instead, set the maximum values for bus elements
of the bus object specified as the data type. For information on the Maximum
parameter for a bus element, see Simulink.BusElement
.
Simulink uses the maximum value to perform:
Parameter range checking (see Specify Minimum and Maximum Values for Block Parameters) for some blocks.
Simulation range checking (see Specify Signal Ranges and Enable Simulation Range Checking).
Automatic scaling of fixedpoint data types.
Optimization of the code that you generate from the model. This optimization can remove algorithmic code and affect the results of some simulation modes such as SIL or external mode. For more information, see Optimize using the specified minimum and maximum values (Embedded Coder).
Note
Output maximum does not saturate or clip the actual output signal. Use the Saturation block instead.
Programmatic Use
Block Parameter:
OutMax 
Type: character vector 
Values: scalar 
Default: '[ ]' 
Output data type — Specify the output data type
Inherit: Inherit via internal
rule
(default)  Inherit: Inherit via back propagation
 Inherit: Same as first input
 double
 single
 half
 int8
 uint8
 int16
 uint16
 int32
 uint32
 int64
 uint64
 fixdt(1,16)
 fixdt(1,16,0)
 fixdt(1,16,2^0,0)
 <data type expression>
Choose the data type for the output. The type can be inherited, specified
directly, or expressed as a data type object such as
Simulink.NumericType
. For more information, see Control Data Types of Signals.
When you select an inherited option, the block behaves as follows:
Inherit: Inherit via internal rule
— Simulink chooses a data type to balance numerical accuracy, performance, and generated code size, while taking into account the properties of the embedded target hardware. If you change the embedded target settings, the data type selected by the internal rule might change. For example, if the block multiplies an input of typeint8
by a gain ofint16
andASIC/FPGA
is specified as the targeted hardware type, the output data type issfix24
. IfUnspecified (assume 32bit Generic)
, in other words, a generic 32bit microprocessor, is specified as the target hardware, the output data type isint32
. If none of the word lengths provided by the target microprocessor can accommodate the output range, Simulink software displays an error in the Diagnostic Viewer.It is not always possible for the software to optimize code efficiency and numerical accuracy at the same time. If the internal rule doesn’t meet your specific needs for numerical accuracy or performance, use one of the following options:
Specify the output data type explicitly.
Use the simple choice of
Inherit: Same as input
.Explicitly specify a default data type such as
fixdt(1,32,16)
and then use the FixedPoint Tool to propose data types for your model. For more information, seefxptdlg
(FixedPoint Designer).To specify your own inheritance rule, use
Inherit: Inherit via back propagation
and then use a Data Type Propagation block. Examples of how to use this block are available in the Signal Attributes library Data Type Propagation Examples block.
Note
When input is a floatingpoint data type smaller than single precision,
Inherit: Inherit via internal rule
depends on the setting of the Inherit floatingpoint output type smaller than single precision configuration parameter. Data types are smaller than single precision when the number of bits needed to encode the data type is less than the 32 bits needed to encode the singleprecision data type. For example,half
andint16
are smaller than single precision.Inherit: Inherit via back propagation
— Use data type of the driving block.Inherit: Same as first input
— Use data type of first input signal.
Programmatic Use
Block Parameter:
OutDataTypeStr 
Type: character vector 
Values: 'Inherit:
Inherit via internal rule  'Inherit: Same as
first input'  'Inherit: Inherit via back
propagation'  'double' 
'single'  'half' 
'int8'  'uint8' 
'int16'  'uint16' 
'int32'  'uint32' 
'int64'  'uint64' 
'fixdt(1,16)' 
'fixdt(1,16,0)' 
'fixdt(1,16,2^0,0)'  '<data type
expression>' 
Default: 'Inherit:
Inherit via internal rule' 
Lock output data type setting against changes by the fixedpoint tools — Prevent fixedpoint tools from overriding data types
off
(default)  on
Select to lock the output data type setting of this block against changes by the FixedPoint Tool and the FixedPoint Advisor. For more information, see Use Lock Output Data Type Setting (FixedPoint Designer).
Programmatic Use
Block Parameter:
LockScale 
Type: character vector 
Values:
'off' 
'on' 
Default:
'off' 
Integer rounding mode — Rounding mode for fixedpoint operations
Floor
(default)  Ceiling
 Convergent
 Nearest
 Round
 Simplest
 Zero
Specify the rounding mode for fixedpoint operations. For more information, see Rounding (FixedPoint Designer).
Block parameters always round to the nearest representable value. To control the rounding of a block parameter, enter an expression using a MATLAB rounding function into the mask field.
Programmatic Use
Block Parameter:
RndMeth 
Type: character vector 
Values:
'Ceiling'  'Convergent'  'Floor'  'Nearest'  'Round'  'Simplest' 
'Zero' 
Default:
'Floor' 
Saturate on integer overflow — Method of overflow action
off
(default)  on
Specify whether overflows saturate or wrap.
off
— Overflows wrap to the appropriate value that the data type can represent.For example, the number 130 does not fit in a signed 8bit integer and wraps to 126.
on
— Overflows saturate to either the minimum or maximum value that the data type can represent.For example, an overflow associated with a signed 8bit integer can saturate to 128 or 127.
Tip
Consider selecting this check box when your model has a possible overflow and you want explicit saturation protection in the generated code.
Consider clearing this check box when you want to optimize efficiency of your generated code.
Clearing this check box also helps you to avoid overspecifying how a block handles outofrange signals. For more information, see Troubleshoot Signal Range Errors.
When you select this check box, saturation applies to every internal operation on the block, not just the output or result.
In general, the code generation process can detect when overflow is not possible. In this case, the code generator does not produce saturation code.
Programmatic Use
Block Parameter: SaturateOnIntegerOverflow 
Type: character vector 
Values: 'off'  'on' 
Default: 'off' 
Block Characteristics
Data Types 

Direct Feedthrough 

Multidimensional Signals 

VariableSize Signals 

ZeroCrossing Detection 

Extended Capabilities
C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.
HDL Code Generation
Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.
HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.
Architecture  Description 

Linear
(default)  Generates a linear chain of adders to compute the sum of products. 
Tree  Generates a tree structure of adders to compute the sum of products. 
General  

InputPipeline  Number of input pipeline stages to insert in the
generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is

OutputPipeline  Number of output pipeline stages to insert in the
generated code. Distributed pipelining and constrained
output pipelining can move these registers. The default is

ConstrainedOutputPipeline  Number of registers to place at the outputs by moving
existing delays within your design. Distributed pipelining
does not redistribute these registers. The default is

Native Floating Point  

HandleDenormals  Specify whether you want HDL Coder to insert additional logic to handle denormal
numbers in your design. Denormal numbers are numbers that
have magnitudes less than the smallest floatingpoint number
that can be represented without leading zeros in the
mantissa. The default is 
LatencyStrategy  Specify whether to map the blocks in your design to

MantissaMultiplyStrategy  Specify how to implement the mantissa multiplication
operation during code generation. By using different
settings, you can control the DSP usage on the target FPGA
device. The default is 
PLC Code Generation
Generate Structured Text code using Simulink® PLC Coder™.
FixedPoint Conversion
Design and simulate fixedpoint systems using FixedPoint Designer™.
Version History
Introduced before R2006a
See Also
MATLAB 명령
다음 MATLAB 명령에 해당하는 링크를 클릭했습니다.
명령을 실행하려면 MATLAB 명령 창에 입력하십시오. 웹 브라우저는 MATLAB 명령을 지원하지 않습니다.
Select a Web Site
Choose a web site to get translated content where available and see local events and offers. Based on your location, we recommend that you select: .
You can also select a web site from the following list:
How to Get Best Site Performance
Select the China site (in Chinese or English) for best site performance. Other MathWorks country sites are not optimized for visits from your location.
Americas
 América Latina (Español)
 Canada (English)
 United States (English)
Europe
 Belgium (English)
 Denmark (English)
 Deutschland (Deutsch)
 España (Español)
 Finland (English)
 France (Français)
 Ireland (English)
 Italia (Italiano)
 Luxembourg (English)
 Netherlands (English)
 Norway (English)
 Österreich (Deutsch)
 Portugal (English)
 Sweden (English)
 Switzerland
 United Kingdom (English)