Partition Motor Control for Multiprocessor MCUs
This example shows how to partition real-time motor control application on to multiple processors to achieve design modularity and improved control performance.
Many MCUs provide multiple processor cores. These additional cores can be leveraged to achieve a variety of design goals:
Divide the application into real-time tasks, such as control laws, and non-real time tasks, such as external communication, diagnostics, or machine learning
Partition the control algorithm to run on multiple CPUs to achieve higher loop rate
Run the same application in multiple CPU's for safety critical applications
This example shows how to partition motor control application across two CPUs of the TI Delfino F28379D to achieve higher sampling time/PWM frequency.
TI Delfino F28379D LaunchPad or TI Delfino F2837xD based board
BOOSTXL-DRV8305EVM motor driver board
Teknic M-2310P-LN-04K PMSM motor
Partition Motor Control Algorithm
Open the soc_pmsm_singlecpu_foc model. This model simulates a single CPU motor controller, contained in the soc_pmsm_singlecpu_ref model, for a permanent magnet synchronous machine (PMSM).
We partition the control algorithm by executing current control on CPU2, and speed control and position estimation on CPU1 respectively. Data transfer between the CPU's are handled by Interprocess Data Channel block. For more information see Interprocess Data Communication via Dedicated Hardware Peripheral (SoC Blockset).
Open the soc_pmsm_dualcpu_foc model.
On the System on Chip tab, click Hardware Settings to open the Configuration Parameters window. In the Hardware Implementation tab, the Processing Unit parameter is configured to "None" indicating it is the top-level system model.
Open the soc_pmsm_cpu1_ref model and open the soc_pmsm_cpu2_ref model to view algorithms configured for each CPU. Model references contained within the system model are configured to run on c28xCPU1 (CPU1) and c28xCPU2 (CPU2).
On the Simulation tab, click Run to simulate the model. Open the Simulation Data Inspector and view signals. This figure shows results from the single and dual CPU models in simulation and deployment.
Performance Improvement with Concurrent Execution
Using both the CPUs to execute control algorithms allows us to achieve higher controller bandwidth. In the original single CPU model, the control algorithm takes just over 25us to execute. To provide a safety margin, single CPU model uses a PWM frequency of 20kHz, equivalent to 50us period.
After partitioning, the CPU1 and CPU2 execution times reduce to less than 20us. Allowing the PWM frequency to be increase to 40kHz. In the
soc_mcb_pmsm_foc_sensorless_f28379d_data.m script, set PWM_frequency to 40e3 and run the script to configure the model to the new PWM frequency. With faster sampling of currents, controller gains can then be tuned to achieve faster response times.
Deploy the model to the TI Delfino F28379D LaunchPad using the SoC Builder (SoC Blockset) tool. To open the tool, on the System on Chip tab, click Configure, Build, & Deploy and follow the guided steps.
This figure shows the controller response from simulation and deployment at 25us current loop with 40kHz PWM frequency compared with 50us current loop at 20kHz frequency. As expected, the rise time in speed improves with faster current loop by approximately 50 percent.
Speed response is oscillatory because of sensorless algorithm, for more information see Sensorless Field-Oriented Control of PMSM
For higher simulation granularity, set the PWM Interface block output to Switching Mode and change the plant model variant to use the MOSFET simulation.
Copyright 2020-2022 The MathWorks, Inc.