Verify Generated HDL Code from MATLAB

R2026b

You can verify the generated HDL code from the design under test (DUT) by using:

• HDL Testbench – Verify the generated code by using a testbench that compares the generated code to the output of the original MATLAB^® function. Testbenhces return pass/fail information. If the outputs of the HDL DUT match the output of the original MATLAB function, the test passes. For more information, see Verify Code with HDL Test Bench (HDL Coder).

• Cosimulation – Verify the generated code by generating an HDL DUT and an hdlverifier.HDLCosimulation System object™, and embedding the object in your MATLAB testbench. To use this option, you must have an HDL Coder™ and an HDL Verifier™ license. For more information, see Verify Generated HDL with Cosimulation.

• FPGA-in-the-Loop – Verify the generated code by generating an HDL DUT and an hdlverifier.FILSimulation (SoC Blockset) System object. To use this option, you must have an HDL Verifier license, and one of the following:

  • HDL Coder Support Package for Intel^® FPGA Boards

  • HDL Coder Support Package for Microchip FPGA and SoC Devices

  • SoC Blockset™ (for AMD)

  For more information, see FIL Simulation with CLI Commands for MATLAB (HDL Coder).

Verify Generated HDL with Cosimulation

When generating HDL from MATLAB using the codegen (MATLAB Coder) function, you can integrate verification with cosimulation. During this workflow, MATLAB performs the following actions:

• Converts the design to use fixed-point math

• Generates HDL from the MATLAB function

• Generates a cosimulation System object, to drive inputs from the MATLAB testbench to the HDL simulation, and extract outputs back from the HDL simulation to the MATLAB testbench.

• Generates a cosimulation testbench, that instantiates the cosimulation System object and interacts with the HDL simulation

• Generates cosimulation scripts

• Executes cosimulation (optional)

Follow these steps to verify generated HDL code with cosimulation:

1. To use fixed-point math, create a coder.FixPtConfig (HDL Coder) object and set the testbench to your testbench function.

   fixptcfg = coder.config("fixpt");
   fixptcfg.TestBenchName = "testbench_name";

2. Create a coder.HdlConfig (HDL Coder) object and set the HDL generation properties.

   hdlcfg = coder.config("hdl");
   hdlcfg.EnableRate = "DUTBaseRate";
   hdlcfg.EnableTraceability = true;
   hdlcfg.TargetLanguage = 'Verilog';
   hdlcfg.Workflow = "Generic ASIC/FPGA";

3. Set the cosimulation properties:

   • Set TestBenchName to the name of the testbench function.

   • If you want to log and plot outputs of the reference design function and HDL simulator, select CosimLogOutputs. This option creates a plot for each output signal, that includes the output from cosimulation, the output from a reference run in MATLAB, and the difference between the two.

   • Set CosimToolto ModelSim, Incisive, Vivado Simulator, or VCS, depending on the HDL simulator you want to use for cosimulation.

   • Set CosimRunMode to Batch mode for non-interactive simulation. Select GUI mode to interact with the HDL simulator and view waveforms (not available for cosimulation with Vivado^®).

   • To run the cosimulation, set SimulateCosimTestBench to true.

   hdlcfg.TestBenchName = "testbench_name";
   hdlcfg.GenerateCosimTestBench = true;
   hdlcfg.SimulateCosimTestBench = true;
   hdlcfg.CosimRunMode = "Batch";
   hdlcfg.CosimTool = "ModelSim";
   hdlcfg.CosimLogOutputs = true;

4. To generate code, cosimulation artifacts, and run cosimulation, use the codegen (HDL Coder) function. Enter this code in the MATLAB command window, where function_name is the name of the function for code generation.

   codegen -float2fixed fixptcfg -config hdlcfg function_name

5. You can also specify advanced options for cosimulation. Set the optional properties according to the descriptions in the following table.

   Parameter	Description
   CosimClockHighTime	Specify the number of nanoseconds the clock is high. The default value is: 5ns
   CosimClockLowTime	Specify the number of nanoseconds the clock is low. The default value is: 5ns
   CosimHoldTime	Specify the hold time for input signals and forced reset signals. The default value is: 2ns
   CosimClockEnableDelay	Specify time (in clock cycles) between deassertion of reset and assertion of clock enable. The default value is: 0
   CosimResetLength	Specify time (in clock cycles) between assertion and deassertion of reset. The default value is: 2

If you set CosimRunMode to Batch, a command window opens, launches the HDL simulator, and runs the cosimulation. The window closes when cosimulation completes. If you set CosimRunMode to GUI, the HDL simulator GUI opens and it remains open after simulation completes so that you can examine the waveforms and other signal data.

For an example that uses codegen to generate HDL and cosimulation, see Verify MATLAB-to-HDL Code by Using Cosimulation and FPGA-in-the-Loop.