You can generate HDL code from a model with both Simulink® and Altera® DSP Builder Advanced blocks using Altera DSP Builder (DSPB) subsystems.
Using both Simulink and Altera blocks in your model provides the following benefits:
A single platform for combined Simulink and Altera DSP Builder simulation, code generation, and synthesis.
Targeted code generation: Altera DSP Builder generates code from Altera blocks; HDL Coder™ generates code from Simulink blocks.
HDL Coder area and speed optimizations for Simulink components.
You must group your Altera blocks into one or more Altera DSP Builder (DSPB) subsystems for code generation. A DSPB subsystem can contain a hierarchy of subsystems.
To generate code from a Altera DSP Builder subsystem, you must use Quartus II 13.0 or later.
A DSPB subsystem is a Subsystem block with:
Architecture set to Module.
A valid DSP Builder Advanced Blockset design, including a top-level Device block and DSP Builder Advanced blocks, as defined in the Altera DSP Builder documentation.
Create an Altera DSP Builder Advanced Blockset design as defined in the Altera DSP Builder documentation.
Create a subsystem containing the Altera DSP
Builder Advanced Blockset design, and set its Architecture to
To see an example that shows HDL code generation for an Altera DSP Builder subsystem, see Using Altera DSP Builder Advanced Blockset with HDL Coder.
DSPB subsystems must either run at the DUT subsystem base rate, or you can provide a custom clock.
Determining the DUT subsystem base rate can be an iterative process. Area optimizations, such as RAM mapping or resource sharing, may cause HDL Coder to oversample area-optimized parts of the design. Therefore, the DUT subsystem initial base rate may differ from the final base rate, and you may not know the model base rate until you generate code.
To determine the model base rate, iteratively generate code until your model converges on a base rate:
Generate code for the DUT subsystem that contains your DSPB subsystem.
If HDL Coder displays an error message that says that your DSPB subsystem rate is slower than the base rate, modify the DSPB subsystem inputs so that the DSPB subsystem runs at the base rate in the message.
For example, you can insert an Upsample block.
Repeat these steps until your DSPB subsystem rate matches the base rate.
To provide a custom clock for your DSPB subsystem:
In the HDL Workflow Advisor, for HDL Code Generation > Set Code Generation Options > Set Advanced Options > Clock inputs, select Multiple.
In the generated HDL code, connect your custom clocks to the DUT clock input ports that corresponds to your DSPB subsystems clock.
Code generation for Altera DSP Builder (DSPB) subsystems has the following limitations:
The DUT subsystem cannot be a DSPB subsystem.
DSPB subsystems must run at the Simulink model base rate. You may need to iteratively generate code to determine the base rate, because area optimizations can cause local multirate. See Determine Clocking Requirements for Altera DSP Builder Subsystems for a workflow.
Altera blocks with bus interfaces are not supported.
Altera DSP Builder does not generate Verilog® code.
Test bench simulation mismatches can occur because the Simulink data comparison does not take Altera valid signals into account. For an example and workaround, see Using Altera DSP Builder Advanced Blockset with HDL Coder.