Dual Rate Dual Port RAM

R2026b

Dual-port RAM that supports two rates

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Dual Rate Dual Port RAM block

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Libraries:
HDL Coder / HDL RAMs

Description

The Dual Rate Dual Port RAM block models a dual-port memory that supports simultaneous read and write operations through two independent RAM ports, port A and port B, which can operate at different rates. Each RAM port has its own address, data, and write-enable signals, which you can use to access different memory locations concurrently. The block ports din_A, addr_A, we_A, and dout_A represent the inputs and outputs for the RAM port A, and ports din_B, addr_B, we_B, and dout_B represent the inputs and outputs for the RAM port B.

In high-performance hardware applications, you can use this block to access the RAM twice per clock cycle. If you generate HDL code, this block maps to a dual-clock dual-port RAM in most FPGAs.

This block supports HDL code generation for complex signals. You cannot mix real-value and complex inputs.

Simultaneous Access

You can access different memory locations in port A and port B simultaneously.

If you access a memory location from one port while the other port writes to the same location, the block generates an error.

Read-During-Write Behavior

The RAM uses write-first behavior. When a write occurs, the newly written data is immediately available at the corresponding output port.

Limitations

• This block does not support the half data type.

• You can generate HDL code for Dual Rate Dual Port RAM blocks that are in resettable subsystems.

• If the RAMArchitecture model configuration parameter is set to WithoutClockEnable, you cannot generate HDL code for Dual Rate Dual Port RAM blocks in enabled or triggered subsystems.

Ports

Input

din_A — Port A write data

scalar (default)

Write data for port A, specified as a scalar. When the signal at port we_A is true, the block writes this data to the memory location specified by port addr_A.

Note

The input signals at ports din_A, addr_A, and we_A must have the same data rate.

Data Types: int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | fixed point | single | double
Complex Number Support: Yes

addr_A — Port A address

scalar (default)

Address for port A, specified as an unsigned scalar with a fraction length of 0. This address identifies the memory location accessed by port A for read or write operations. The address width must be between 2 and 28 bits.

Data Types: uint8 | uint16 | fixed point

we_A — Port A write-enable signal

scalar (default)

Write-enable signal for port A, specified as a scalar. The we_A signal determines whether the block writes or reads data:

• When the signal at port we_A is true, the block writes data from the din_A port to the memory location specified by the addr_A port.

• When the signal at port we_A is false, the block reads data from the memory location specified by the addr_A port.

Data Types: Boolean

din_B — Port B write data

scalar (default)

Write data for port B, specified as a scalar. When the signal at port we_B is true, the block writes this data to the memory location specified by port addr_B.

Note

The input signals at ports din_B, addr_B, and we_B must have the same data rate.

Data Types: int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | fixed point | single | double
Complex Number Support: Yes

addr_B — Port B address

scalar (default)

Address for port B, specified as an unsigned scalar with a fraction length of 0. This address identifies the memory location accessed by port B for read or write operations. The address width must be between 2 and 28 bits.

Data Types: uint8 | uint16 | fixed point

we_B — Port B write-enable signal

Scalar (default)

Write-enable signal for port B, specified as a scalar. The we_B signal determines whether the block writes or reads data:

• When the signal at port we_B is true, the block writes data from the din_B port to the memory location specified by the addr_B port.

• When the signal at port we_B is false, the block reads data from the memory location specified by the addr_B port.

Data Types: Boolean

Output

dout_A — Port A output data

scalar (default)

Read data output for port A, returned as a scalar. This output is the data read from the memory location specified by the addr_A port.

Data Types: int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | fixed point | single | double
Complex Number Support: Yes

dout_B — Port B output data

scalar (default)

Read data output from port B, returned as a scalar. This output is the data read from the memory location specified by the addr_B port.

Data Types: int8 | int16 | int32 | int64 | uint8 | uint16 | uint32 | uint64 | fixed point | single | double
Complex Number Support: Yes

Parameters

Address port width — Address bit width

8 (default) | integer

Address of the bit width that the memory uses. The value must be an integer between 2 and 28.

Programmatic Use

Block parameter: ram_size

Type: string scalar | character vector

Value:Integer between 2 and 28

Default: '8'

Algorithms

HDL code generated for RAM blocks has:

• A latency of one clock cycle for read data output.

• No reset signal, because some synthesis tools do not infer a RAM from HDL code if it includes a reset.

RAM Initialization

Only use generated code to initialize a RAM during simulation. Synthesis tools can ignore this code.

Implement RAM With or Without Clock Enable

If the RAM block is in a subsystem, you can use the RAM Architecture model configuration parameter to control the clock enable logic:

• Setting this parameter to RAM with clock enable generates a RAM by using HDL templates that use a clock enable signal, and an empty RAM wrapper.

• Setting this parameter to Generic RAM without clock enable generates RAM without a clock enable and uses a RAM wrapper that implements the clock enable logic.

Some synthesis tools do not infer RAM structures that include clock enable signals. If your synthesis tool does not support RAM structures with a clock enable signals, and cannot map the generated HDL code to FPGA RAM resources, set RAM Architecture parameter to Generic RAM without clock enable.

RAM Inference Limitations

If you perform concurrent read and write operations, verify the read-during-write behavior in the hardware. The read-during-write behavior of the RAM blocks matches the behavior of the generated HDL code. However, if your synthesis tool does not follow the same behavior during RAM inference, the read-during-write behavior in the hardware can differ from the behavior of the Simulink^® model or generated HDL code.

Your synthesis tool might not map the generated code to RAM for these reasons:

• Small RAM size: To achieve better performance, the synthesis tool might implement a small RAM using registers.

• Clock enable signal present: You can suppress clock enable generation by using the RAM Architecture model configuration parameter. For more information, see Get Started with RAM and ROM in Simulink.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation

Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

Note

To match simulation results with the generated HDL code, enable single-task mode by clearing the Treat each discrete rate as a separate task model configuration parameter in the Solver settings. When you select this option, simulation can update outputs in the same cycle, but the generated HDL updates outputs one cycle later.

This block has one default HDL architecture.

HDL Block Properties

General
ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays in the design. Distributed pipelining does not redistribute these registers. The default value is 0. For more details, see ConstrainedOutputPipeline.
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default value is 0. For more details, see InputPipeline.
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default value is 0. For more details, see OutputPipeline.
SynthesisAttributes	Specifies the synthesis attributes for the blocks and block output signals in the model. The generated HDL code contains these attributes. For more information, see SynthesisAttributes.

Note

The RAMDirective property is not available for use with the Dual Rate Dual Port RAM because the block does not have a single clock interface.

Optimizations

You can use speed and area optimizations in HDL Coder to generate HDL code from Simulink models that meets your design requirements for speed, area, and throughput while preserving the functional behavior. These optimizations can introduce additional latency or cause differences in sample rates. In Simulink, you can apply optimizations at the model, subsystem, or individual block level. For more information about the available optimizations in HDL Coder, see Introduction to Optimizations in HDL Coder.

Version History

Introduced in R2014a

R2026a: Specify synthesis attributes for blocks and block output signals

Use the SynthesisAttributes HDL block property to specify the synthesis attributes for the block and its output signals. HDL Coder includes these attributes in the generated HDL code.