Main Content

Register Count nvlink Error

Issue

The NVIDIA compiler (nvcc) may fail in the linking stage due to a mismatch in the maximum number of registers computed at compilation. A generated CUDA kernel is compiled with a max register count decided by NVCC. A kernel may call a device function in a different CUDA file. The device function may be compiled to use a larger number of registers exceeding the max register count of the kernel.

You may encounter an error message with the following pattern:

nvlink error : entry function 'xxx' with max regcount of n calls function 'yyy' with regcount of m.

nvlink error : entry function 'xx' with max 
regcount of n calls function 'yyy' with 
regcount of m.

where 'xxx' and 'yyy' are the mangled function names, n and m are integers, and m is larger than n.

Possible Solutions

Use the '-maxrregcount n' compiler flag of NVCC to specify the maximum amount of registers. Use the compiler flags option in the GPU code configuration parameters to pass compiler flags to NVCC. For example,

cfg = coder.gpuConfig;
cfg.GpuConfig.compilerFlags = '-maxrregcount n';

where n is the smallest integer number of register count in the error message thrown by nvlink.