Complex Burst Q-less QR Decomposition with Forgetting Factor Whole R Output

Q-less QR decomposition for complex-valued matrices with infinite number of rows

Since R2022b

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Libraries:
Fixed-Point Designer HDL Support / Matrices and Linear Algebra / Matrix Factorizations

Description

The Complex Burst Q-less QR Decomposition with Forgetting Factor Whole R Output block uses QR decomposition to compute the economy size upper-triangular R factor of the QR decomposition, A = QR, without computing Q. A is an infinitely tall complex-valued matrix representing streaming data.

When the regularization parameter is nonzero, the Complex Burst Q-less QR Decomposition with Forgetting Factor Whole R Output block initializes the first upper-triangular factor R to λI_n before factoring in the rows of A, where λ is the regularization parameter and I_n = eye(n)

Examples

Implement Hardware-Efficient Complex Burst Q-less QR with Forgetting Factor

Use the hardware-efficient Complex Burst Q-less QR Decomposition with Forgetting Factor Whole R Output block.

• Open Script

Ports

Input

A(i,:) — Rows of complex matrix A

vector

Rows of complex matrix A, specified as a vector. A is an infinitely tall matrix of streaming data. If A uses a fixed-point data type, A must be signed and use binary-point scaling. Slope-bias representation is not supported for fixed-point data types.

Data Types: single | double | fixed point

validIn — Whether inputs are valid

Boolean scalar

Whether inputs are valid, specified as a Boolean scalar. This control signal indicates when the data from the A(i,:) input port is valid. When this value is 1 (true) and the value of ready is 1 (true), the block captures the values at the A(i,:) input port. When this value is 0 (false), the block ignores the input samples.

After sending a true validIn signal, there may be some delay before ready is set to false. To ensure all data is processed, you must wait until ready is set to false before sending another true validIn signal.

Data Types: Boolean

restart — Whether to clear internal states

Boolean scalar

Whether to clear internal states, specified as a Boolean scalar. When this value is 1 (true), the block stops the current calculation and clears all internal states. When this value is 0 (false) and the value at validIn is 1 (true), the block begins a new subframe.

Data Types: Boolean

Output

R — Economy size QR decomposition matrix R

vector

Economy size QR decomposition matrix R, returned as a vector. R is an upper triangular matrix. The size of matrix R is n-by-n. R has the same data type as A.

Data Types: single | double | fixed point

validOut — Whether output data is valid

Boolean scalar

Whether the output data is valid, specified as a Boolean scalar. This control signal indicates when the data at output port R(i,:) is valid. When this value is 1 (true), the block has successfully computed the matrix R. When this value is 0 (false), the output data is not valid.

Data Types: Boolean

ready — Whether block is ready

Boolean scalar

Whether the block is ready, returned as a Boolean scalar. This control signal indicates when the block is ready for new input data. When this value is 1 (true) and validIn is 1 (true), the block accepts input data in the next time step. When this value is 0 (false), the block ignores input data in the next time step.

After sending a true validIn signal, there may be some delay before ready is set to false. To ensure all data is processed, you must wait until ready is set to false before sending another true validIn signal.

Data Types: Boolean

Parameters

Number of columns in matrix A — Number of columns in input matrix A

4 (default) | positive integer-valued scalar

Number of columns in input matrix A, specified as a positive integer-valued scalar.

Programmatic Use

Block Parameter: n

Type: character vector

Values: positive integer-valued scalar

Default: 4

Forgetting factor — Forgetting factor applied after each row of the matrix is factored

0.99 (default) | real positive scalar

Forgetting factor applied after each row of the matrix is factored, specified as a real positive scalar. The output is updated as each row of A is input indefinitely.

Programmatic Use

Block Parameter: forgetting_factor

Type: character vector

Values: real positive scalar

Default: 0

Regularization parameter — Regularization parameter

0 (default) | real nonnegative scalar

Regularization parameter, specified as a real nonnegative scalar. Small, positive values of the regularization parameter can improve the conditioning of the problem and reduce the variance of the estimates. While biased, the reduced variance of the estimate often results in a smaller mean squared error when compared to least-squares estimates.

Programmatic Use

Block Parameter: regularizationParameter

Type: character vector

Values: real nonnegative scalar

Default: 0

Algorithms

Choosing the Implementation Method

Systolic implementations prioritize speed of computations over space constraints, while burst implementations prioritize space constraints at the expense of speed of the operations. The following table illustrates the tradeoffs between the implementations available for matrix decompositions and solving systems of linear equations.

Implementation	Throughput	Latency	Area
Systolic	C	O(n)	O(mn2)
Partial-Systolic	C	O(m)	O(n2)
Partial-Systolic with Forgetting Factor	C	O(n)	O(n2)
Burst	O(n)	O(mn)	O(n)

Where C is a constant proportional to the word length of the data, m is the number of rows in matrix A, and n is the number of columns in matrix A.

For additional considerations in selecting a block for your application, see Choose a Block for HDL-Optimized Fixed-Point Matrix Operations.

AMBA AXI Handshake Process

This block uses the AMBA AXI handshake protocol [1]. The valid/ready handshake process is used to transfer data and control information. This two-way control mechanism allows both the manager and subordinate to control the rate at which information moves between manager and subordinate. A valid signal indicates when data is available. The ready signal indicates that the block can accept the data. Transfer of data occurs only when both the valid and ready signals are high.

Block Timing

The Burst Q-less QR Decomposition with Forgetting Factor Whole R Output blocks accept and process the matrix A row by row. After accepting the first m rows, the block starts to output the R matrix as a vector. Then, for each row input, the block calculates an R matrix.

For example, assume that the input A matrix is 3-by-3. Additionally assume that validIn asserts before ready, meaning that the upstream data source is faster than the QR decomposition.

In the figure,

• A1r1 is the first row of the first A matrix, R1 is the first R matrix, and so on.

• validIn to ready — From a successful row input to the block being ready to accept the next row.

• validIn to validOut — From a successful row input to the block starting to output the corresponding solution.

• validOut to ready — From the block starting to output the solution to the block ready to accept the next matrix input.

The following table provides details of the timing for the Burst Q-less QR Decomposition with Forgetting Factor Whole R Output blocks.

Block	validIn to ready (cycles)	validIn to validOut (cycles)	validOut to ready (cycles)
Real Burst Q-less QR Decomposition with Forgetting Factor Whole R Output	(wl + 5)*n + 2 + n	(wl + 5)*n + 2 + n - 1	1
Complex Burst Q-less QR Decomposition with Forgetting Factor Whole R Output	(wl*2 + 11)*n + 2 + n	(wl*2 + 11)*n + 2 + n - 1	1

In the table, m represents the number of rows in matrix A, and n is the number of columns in matrix A. wl represents the word length of A.

• If the data type of A is fixed point, then wl is the word length.

• If the data type of A is double, then wl is 53.

• If the data type of A is single, then wl is 24.

Hardware Resource Utilization

This block supports HDL code generation using the Simulink^® HDL Workflow Advisor. For an example, see HDL Code Generation and FPGA Synthesis from Simulink Model (HDL Coder) and Implement Digital Downconverter for FPGA (DSP HDL Toolbox).

This example data was generated by synthesizing the block on a Xilinx^® Zynq^® UltraScale™ + RFSoC ZCU111 evaluation board. The synthesis tool was Vivado^® v.2020.2 (win64).

The following parameters were used for synthesis.

• Block parameters:

  • n = 16

  • Matrix A dimension: inf-by-16

• Input data type: sfix16_En14

• Target frequency: 300 MHz

The following tables show the post place-and-route resource utilization results and timing summary, respectively.

Resource	Usage	Available	Utilization (%)
CLB LUTs	21142	425280	4.97
CLB Registers	21158	850560	2.49
DSPs	32	4272	0.75
Block RAM Tile	0	1080	0.00
URAM	0	80	0.00

	Value
Requirement	3.3333 ns
Data Path Delay	3.051 ns
Slack	0.264 ns
Clock Frequency	325.80 MHz

References

[1] "AMBA AXI and ACE Protocol Specification Version E." https://developer.arm.com/documentation/ihi0022/e/AMBA-AXI3-and-AXI4-Protocol-Specification/Single-Interface-Requirements/Basic-read-and-write-transactions/Handshake-process

Extended Capabilities

C/C++ Code Generation

Generate C and C++ code using Simulink® Coder™.

Slope-bias representation is not supported for fixed-point data types.

HDL Code Generation

Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

General
ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see OutputPipeline (HDL Coder).

Restrictions

Supports fixed-point data types only.

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

Version History

Introduced in R2022b