Main Content

Peripheral Management

R2026b
Configure Infineon® AURIX™ TC3x microcontrollers using blocks, Hardware Mapping tool, and configuration parameter settings

Before communicating with the target hardware, first apply block settings, hardware configuration parameters, and Hardware Mapping tool settings.

Blocks

expand all

Digital Port Read block iconDigital Port ReadRead GPIO pin(s) status (Since R2024a)
Digital Port Write block iconDigital Port WriteSet GPIO pin(s) status (Since R2024a)
Hardware Interrupt blockHardware InterruptTrigger downstream function-call subsystem from an interrupt service routine (Since R2022b)
Encoder Block iconEncoderMeasures rotation of motor in ticks (Since R2024a)
EVADC block iconEVADCMeasure voltage of an analog input pin (Since R2024a)
PWM block iconPWMGenerate pulse width modulated waveforms (Since R2024a)
QSPI controllerl block iconQSPI ControllerWrite data to and read data from an SPI peripheral device (Since R2024a)
QSPI peripheral block iconQSPI PeripheralWrite data to and read data from an SPI controller device (Since R2024a)
EDSADC block iconEDSADCMeasure voltage of analog input pin using delta-sigma conversion (Since R2024b)
SENT block iconSENTRead high-resolution sensor data over Single Edge Nibble Transmission (SENT) protocol (Since R2024b)
MCAN Transmit blockMCAN TransmitWrite data to CAN bus (Since R2025a)
MCAN Receive Block iconMCAN ReceiveRead data from CAN bus (Since R2025a)
TC3x Serial Transmit block iconSerial TransmitWrite data to the UART port (Since R2026b)
TC3x Serial Receive block iconSerial ReceiveRead data from the UART port (Since R2026b)
Byte Pack blockByte PackConvert input signals to 8-, 16-, or 32-bit vector
Byte Unpack blockByte UnpackUnpack 8-, 16-, or 32-bit input vector to multiple output vectors
Byte ReversalReverse little-endian data for big-endian processor
Memory CopyCopy to and from memory section
CAN Pack blockCAN PackPack individual signals into CAN message
CAN Unpack blockCAN UnpackUnpack individual signals from CAN messages
CAN FD Pack blockCAN FD PackPack individual signals into message for CAN FD bus
CAN FD Unpack blockCAN FD UnpackUnpack individual signals from CAN FD messages
Block icon of ADC Interface.ADC InterfaceConvert analog signal on ADC input pin to digital signal
Block icon of PWM Interface.PWM InterfaceSimulate pulse width modulation (PWM) output from hardware
Digital I/O InterfaceDigital IO InterfaceSimulate digital input and output pins on processor
Block icon of interprocess data read.Interprocess Data ReadReceive messages from another processor using interprocess communication channel
Interprocess Data WriteSend messages to another processor using interprocessor data write
Block icon of interprocess data channel.Interprocess Data ChannelModel interprocessor data channel between two processors
Task Manager blockTask ManagerCreate and manage task executions in Simulink model
Event Source blockEvent SourceSimulate and playback recorded task events

Tools

SoC BuilderBuild, load, and execute multicore application models on Infineon AURIX TC4x hardware boards (Since R2024b)
Hardware MappingMap tasks and peripherals in a model to hardware board configurations (Since R2022b)
Digital Port Read Peripheral ConfigurationMap Digital Port Read peripherals in the Infineon AURIX model to peripheral registers in the MCU (Since R2024a)
Digital Port Write Peripheral ConfigurationMap Digital Port Write peripherals in the Infineon AURIX model to peripheral registers in the MCU (Since R2024a)
TasksMap tasks in the Infineon AURIX to interrupt service routines on the hardware board (Since R2024a)
Encoder Peripheral ConfigurationMap encoder peripherals in the Infineon AURIX model to peripheral registers in the MCU (Since R2024a)
EVADC Peripheral ConfigurationMap EVADC peripherals in the Infineon AURIX model to peripheral registers in the MCU (Since R2024a)
PWM Peripheral ConfigurationMap PWM peripherals in the Infineon AURIX model to peripheral registers in the MCU (Since R2024a)
QSPI Controller Peripheral ConfigurationMap QSPI controller peripherals in the Infineon AURIX model to peripheral registers in the MCU (Since R2024a)
QSPI Peripheral ConfigurationMap QSPI peripherals in the Infineon AURIX model to peripheral registers in the MCU (Since R2024a)
EDSADC Peripheral ConfigurationMap EDSADC peripherals in Infineon AURIX model to peripheral registers in MCU (Since R2024b)
SENT ConfigurationMap data transfer over SENT protocol in the Infineon AURIX model to peripheral registers in the MCU (Since R2024b)
MCAN Transmit Peripheral ConfigurationMap peripherals of MCAN Transmit block in the model to peripheral registers in MCU (Since R2025a)
MCAN Receive Peripheral ConfigurationMap MCAN Receive peripherals in the model to the peripheral registers in MCU (Since R2025a)
Serial Peripheral ConfigurationConfigure Serial Transmit block and Serial Receive block peripherals (Since R2026b)

Topics

Featured Examples