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DSP HDL IP Designer

Configure and generate HDL code for digital signal processing IPs

Since R2024b

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Description

Select a digital signal processing (DSP) algorithm and configure parameters and input stimulus. Then, generate HDL code and a testbench to verify the behavior of your design.

The DSP HDL IP Designer app provides hardware-optimized algorithms that have streaming data interfaces and hardware-friendly control signals. The algorithms can use frame-based input and parallel operations to achieve gigasamples-per-second (GSPS) data rates, also called super sample rates. You can change the algorithm parameters to explore and generate different hardware implementations. The app supports HDL code generation with HDL Coder™ and optional HDL testbench generation.

After you select your algorithm and set its parameters, click on the Input Stimulus block to configure input data signals. The dimensions and data types of these values define your HDL interface, and the generated testbench applies these values to your algorithm. You do not have to specify stimulus for input control signals. The app provides default values for each input port, assigned as fields in the testbench structure. You must use the same field names as the default stimulus.

The testbench.data input must be a 1-D or 3-D matrix in the data type you want your HDL IP to use. For example:

  • testbench.data = uint8(1:1:1024) is a 1-D matrix that represents 1024 uint8 input samples with one input sample per cycle.

  • testbench.data = reshape(uint8(1:1:1024),4,1,[]) is a 3-D matrix, with dimensions 4-by-1-by-256, that represents an input frame size of 4 samples per cycle for 256 cycles.

Other input signals can be scalars or vectors. For example:

  • testbench.coeff = fi(fir1(17,0.1),1,16) is a filter coefficients input, specified as a 1-by-17 vector of 16-bit fixed-point values.

  • testbench.R = fi(2,0,12,0) is a decimation factor input, specified as a scalar 12-bit integer value.

DSP HDL IP Designer app toolstrip

You can configure and generate HDL code for one algorithm at a time.

To configure HDL code generation options, including enabling generation of an HDL simulator testbench, click Configure HDL. Then, to generate code, click Generate HDL.

To generate a SystemVerilog DPI component, select Generate DPI Component from the Generate HDL pull-down menu. You can integrate this component into your HDL simulation as a behavioral model. You must have the HDL Verifier™ product to use the Generate DPI Component feature.

After you generate HDL code, you can see output log messages in the CONSOLE tab and a hardware resources estimate in the RESOURCES tab.

DSP HDL IP Designer app

Open the DSP HDL IP Designer App

  • Find the app in the Signal Processing and Communications

    group in the Apps gallery.

  • At the MATLAB® command prompt, enter this command.

    dsphdlIPDesigner

Examples

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This example uses:

Open Live Script

This example shows how to configure a discrete FIR filter and generate HDL code in the DSP HDL IP Designer app.

To generate HDL IP core for an algorithm in the DSP HDL IP Designer app:

  1. Select an algorithm and set its parameters.

  2. Configure input dimensions and data types.

  3. Generate HDL code and optional testbench.

This example shows designs for a fully-parallel FIR filter with high throughput and a partly-serial FIR filter that uses fewer resources and has lower throughput. For details of filter implementation options, see FIR Filter Architectures for FPGAs and ASICs. Each IP block in the app provides the same implementation, ports, and parameters as the Simulink® library block for the same algorithm. For more information about the ports and parameters of each algorithm, refer to the block reference pages. For example, see Discrete FIR Filter.

Find the DSP HDL IP Designer app in the Signal Processing and Communications group in the Apps gallery. Or, at the MATLAB® command prompt, enter this command.

dsphdlIPDesigner

Select an Algorithm

Select the Discrete FIR Filter from the IP BLOCKS gallery in the app.

The algorithms all have streaming interfaces with a data port and a control signal that indicates when the input data is valid. The data ports accept and return a scalar or small vector of input data samples on each clock cycle. In the app, you can see the interface signals connecting the IP block to the Input Stimulus block.

To configure your algorithms, set options in the Properties sidebar. Setting the Filter Structure parameter to Direct-form systolic implements a fully-parallel filter with high throughput. Configure the filter coefficients as a 25-tap lowpass FIR filter by setting the Coefficients parameter to firpm(24,[0 .1 .3 .5]*2,[1 1 0 0]). The coefficients are specified in double data type, and by default the filter casts them to match the input data type. You can also specify a coefficient data type on the Data Types tab.

Configure Input Stimulus

Click the Input Stimulus block. The Input settings section in the Properties sidebar provides dimensions and data types for the input to the algorithm. The app provides default values for each input port. The dimensions and data types of these values define your HDL interface, and generated testbench applies these values to your algorithm. You do not need to specify values for control signals like valid and reset. The generated testbench automatically drives the control signals. For this algorithm, you must specify the data input.

The data input for this FIR filter can be a 1-D or 3-D matrix. A 1-D matrix represents a stream of data samples over time. A 3-D matrix specifies number of input samples per cycle-by-number of data channels-by-data samples over time. The Discrete FIR Filter algorithm supports frame-based data, or multichannel data, but not both at the same time.

This example specifies a 1-D matrix that represents 200 fixed-point data type input samples. This data format configures the filter to accept one input sample each clock cycle and the filter has a single data channel.

numSamples = 200;
testbench.data = fi(randn(numSamples,1),1,16,15);

Alternatively, to configure the filter to accept a frame of four input samples each clock cycle, you can set the input data to a 4-by-1-by-data samples over time matrix. A filter with frame-based input must have a single data channel. A filter with 4-sample vector input implements a polyphase decomposition into 4 parallel subfilters, and does not implement symmetry optimizations. This implementation uses more resources to support increased throughput. 

numSamples = 200;
dataIn = fi(randn(numSamples,1),1,16,15);
testbench.data = reshape(dataIn,4,1,[]);

To specify a multichannel filter, first set the Coefficients parameter to a number of channels-by-coefficients matrix, like [firpm(24,[0 .1 .3 .5]*2,[1 1 0 0]); firpm(24,[0 .1 .2 .4]*2,[1 1 0 0])]. Then, configure the input stimulus as a 3-D matrix of 1-by-number of channels-by-data samples over time values. A filter with multiple channels cannot use frame-based input. Each channel accepts a single sample each cycle. This filter uses the same resources as the scalar input filter. 

numSamples = 200;
dataIn = fi(randn(numSamples,1),1,16,15);
testbench.data = reshape(dataIn,1,2,[]);

Generate HDL Code

You can configure HDL code generation options in Configure HDL. By default, the app generates an HDL simulator testbench and scripts for compiling and running the design in Siemens® ModelSim® and AMD® Vivado®. The HDL simulator testbench applies the input signals you defined in Input Stimulus, drives the input control signals, and compares all the output ports of the generated HDL IP against the output from running your algorithm in a MATLAB® simulation.

To generate HDL code and testbench, click Generate HDL. The code generation log appears in the CONSOLE window. If there is a warning or error, it will appear in the CONSOLE window.

The generated files and reports are under codegen\hdl_IP\hdlsrc in your working folder. You can find more information about any errors or warnings in the hdl_IP_hdl_conformance_report.html file.

The generated VHDL entity shows the IP interface including control signals and the input data type you specified. The output data type is determined by the Output parameter on the Data Type tab of the algorithm. By default, it is derived from the input data type with no loss of precision.

The RESOURCES tab shows an estimate of hardware resources used by this filter implementation. A filter with scalar input shares multipliers between symmetric coefficients, so this 25-tap filter uses 13 multipliers.

Serial Filter Implementation

To implement a filter that uses fewer resources but has lower throughput, you can select a serial implementation. On the Discrete FIR Filter in the app, set the Structure parameter to Partly-serial systolic. Then, you can specify the serialization by either the number of multipliers or number of cycles between valid input samples. For a filter with L coefficients, the IP implements a serial filter with M or fewer multipliers and requires input samples that are at least N cycles apart, such that L = N×M. To implement a fully serial filter, select Minimum number of cycles between valid input samples and set Number of cycles to 13 (the number of multupliers used by the scalar input filter previously described).

When you apply these changes, the block in the app now has an output ready port which indicates when the filter is ready for new input data. The generated HDL testbench automatically responds to the ready signal and spaces the input data samples the correct number of cycles apart. You do not have to change your Input Stimulus settings for this implementation.

After you generate HDL code, you can see the updated resource estimate in the RESOURCES tab. This implementation uses only one multiplier but has slower throughput than the parallel filter because samples can only be applied every 13 cycles. The single multiplier is shared in time between the symmetry-optimized coefficients.

This example showed how you can use the app to explore hardware implementations of algorithms without constructing a model or script to run the algorithm. You can quickly generate HDL code and testbench components for your algorithms, and assess the hardware resource use of your IP.

Parameters

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Each IP block in the app provides the same implementation, ports, and parameters as the Simulink® library block for the same algorithm. For more information about the ports and parameters of each algorithm, refer to the block reference pages, Blocks.

To access the parameters shown here, click Configure HDL in the toolbar.

Select the language (VHDL® or Verilog®) in which code is generated. The generated HDL code complies with these standards:

  • VHDL-1993 (IEEE® 1076-1993)

  • Verilog-2001 (IEEE 1364-2001)

File name of generated HDL code, specified as a character vector or a string scalar. The coder adds a file type extension to the file name to match the language you select. The file name also determines the name of the generated VHDL entity or Verilog module.

The test bench applies the input signals from the Input Stimulus block to the generated HDL code and compares the output with captured results from a MATLAB simulation.

Specify the active clock edge that triggers Verilog or always blocks or VHDL process blocks in the generated HDL code.

  • Rising — The rising edge, or 0-to-1 transition, is the active clock edge.

  • Falling — The falling edge, or 1-to-0 transition, is the active clock edge.

Specify whether to use asynchronous or synchronous reset logic when generating HDL code for registers.

  • Asynchronous — The reset logic does not check for an active clock before performing a reset. This VHDL process block shows an asynchronous reset. When the reset signal is asserted, the process block performs a reset without checking for a clock event.

    Unit_Delay1_process : PROCESS (clk, reset)
  BEGIN
    IF reset = '1' THEN
      Unit_Delay1_out1 <= (OTHERS => '0');
    ELSIF clk'event AND clk = '1' THEN
      IF clk_enable = '1' THEN
        Unit_Delay1_out1 <= signed(x_in);
      END IF;
    END IF; 
  END PROCESS Unit_Delay1_process;

  • Synchronous — The reset logic checks for an active clock before performing a reset. This VHDL process block checks for a clock event, in this case the rising edge, before performing a reset:

    Unit_Delay1_process : PROCESS (clk)
  BEGIN
    IF rising_edge(clk) THEN
      IF reset = '1' THEN
        Unit_Delay1_out1 <= (OTHERS => '0');
      ELSIF clk_enable = '1' THEN
        Unit_Delay1_out1 <= signed(x_in);
      END IF;
    END IF; 
  END PROCESS Unit_Delay1_process;

Specify whether the asserted or active level of the reset input signal is active-high or active-low. When you select Active-high, to reset registers in the design, you must set the reset input signal to 1 (true). When you select Active-low, to reset registers in the design, you must set the reset input signal to 0 (false).

Selecting your FPGA vendor-allows the filter to match hardware details of the DSP blocks when adding pipeline registers to the architecture. Vendor-specific multiplier, pipeline register, and pre-adder locations help fit the filter design to the DSP blocks on the FPGA.

The coder generates compilation scripts for Siemens® ModelSim™ and AMD® Vivado®. If the Include testbench parameter is selected, the coder also generates compilation and simulation scripts for the testbench.

Version History

Introduced in R2024b

See Also

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