Variable FIR Decimation
Libraries:
DSP System Toolbox /
Filtering /
Multirate Filters
Description
The Variable FIR Decimation block performs an efficient polyphase FIR decimation with a tunable decimation factor. You can update the decimation factor and the filter coefficients in the block dialog box or through an input port while the simulation is running. To control the decimation, you can specify the decimation factor or the output frame length.
When you specify the decimation factor, if the input frame length changes (variablesize signal) during simulation, the output frame length also changes in order to keep the decimation factor constant. When you specify the output frame length instead of the decimation factor, and if the input frame length changes (variablesize signal) during simulation, the decimation factor also changes in order to keep the output frame length constant.
Conceptually, the FIR decimator (as shown in the schematic) consists of an antialiasing
FIR filter followed by a downsampler. To design an FIR antialiasing filter, use the designMultirateFIR
function.
The FIR filter filters the data in each channel of the input using a directform FIR filter. The downsampler that follows downsamples each channel of filtered data by taking every Mth sample and discarding the M – 1 samples that follow. M is the value of the decimation factor. The resulting discretetime signal has a sample rate that is 1/M times the original sample rate.
Note that the actual block algorithm implements a directform FIR polyphase structure, an efficient equivalent of the combined system depicted in the diagram. For more details, see Algorithms.
The block supports C and C++ code generation.
Examples
Ports
Input
Output
Parameters
Block Characteristics
Data Types 

Direct Feedthrough 

Multidimensional Signals 

VariableSize Signals 

ZeroCrossing Detection 

More About
Algorithms
The FIR decimation filter is implemented efficiently using a polyphase structure. For more information on polyphase filters, see Polyphase Subfilters.
To derive the polyphase structure, start with the transfer function of the FIR filter
$$H(z)={b}_{0}+{b}_{1}{z}^{1}+\mathrm{...}+{b}_{N}{z}^{N},$$
where N+1 is the length of the FIR filter.
You can rearrange this equation as
$$H(z)=\begin{array}{c}\left({b}_{0}+{b}_{{M}_{\text{max}}}{z}^{{M}_{\text{max}}}+{b}_{2{M}_{\text{max}}}{z}^{2{M}_{\text{max}}}+\mathrm{...}+{b}_{N{M}_{\text{max}}+1}{z}^{(N{M}_{\text{max}}+1)}\right)+\\ {z}^{1}\left({b}_{1}+{b}_{{M}_{\text{max}}+1}{z}^{{M}_{\text{max}}}+{b}_{2{M}_{\text{max}}+1}{z}^{2{M}_{\text{max}}}+\mathrm{...}+{b}_{N{M}_{\text{max}}+2}{z}^{(N{M}_{\text{max}}+1)}\right)+\\ \begin{array}{c}\vdots \\ {z}^{({M}_{\text{max}}1)}\left({b}_{{M}_{\text{max}}1}+{b}_{2{M}_{\text{max}}1}{z}^{{M}_{\text{max}}}+{b}_{3{M}_{\text{max}}1}{z}^{2{M}_{\text{max}}}+\mathrm{...}+{b}_{N}{z}^{(N{M}_{\text{max}}+1)}\right),\end{array}\end{array}$$
where M_{max} is the number of polyphase components, and its value equals the maximum decimation factor.
You can write H(z) as
$$H(z)={E}_{0}({z}^{{M}_{\text{max}}})+{z}^{1}{E}_{1}({z}^{{M}_{\text{max}}})+\mathrm{...}+{z}^{({M}_{\text{max}}1)}{E}_{{M}_{\text{max}}1}({z}^{{M}_{\text{max}}}),$$
where E_{0}(z^{Mmax}), E_{1}(z^{Mmax}), ..., E_{Mmax1}(z^{Mmax}) are the polyphase components of the FIR filter H(z).
During simulation, the algorithm reconstructs the filter H(z) based on the current decimation factor M.
Rewriting H(z) in terms of the decimation factor M yields
$$H(z)=r{E}_{0}({z}^{M})+{z}^{1}r{E}_{r}({z}^{M})+\mathrm{...}+{z}^{(M1)}r{E}_{(M1)r}({z}^{M}),$$
where r = M_{max}/M.
Conceptually, the FIR decimation filter contains a lowpass FIR filter followed by a downsampler.
Replace H(z) with its polyphase representation.
This is the multirate noble identity for decimation.
Applying the noble identity for decimation moves the downsampling operation to before the filtering operation. This move enables you to filter the signal at a lower rate.
You can replace the delays and the decimation factor at the input with a commutator switch. The switch starts on the first branch 0 and moves in the counterclockwise direction as shown in this diagram. The accumulator at the output receives the processed input samples from each branch of the polyphase structure and accumulates these processed samples until the switch goes to branch 0. When the switch goes to branch 0, the accumulator outputs the accumulated value.
When the first input sample is delivered, the switch feeds this input to the branch 0 and the decimator computes the first output value. As more input samples come in, the switch moves in the counter clockwise direction through branches (M−1)r, (M−2)r, and all the way up to branch 0, delivering one sample at a time to each branch. When the switch comes to branch 0, the decimator outputs the next set of output values. This process continues as data keeps coming in. Every time the switch comes to the branch 0, the decimator outputs y[m]. The decimator effectively outputs one sample for every M samples it receives. Hence the sample rate at the output of the FIR decimation filter is fs/M.
References
[1] Orfanidis, Sophocles J. Introduction to Signal Processing. Upper Saddle River, NJ: PrenticeHall, 1996.