MATLAB and Simulink Seminars

Algorithm to Silicon Forum: Driving Cross-Functional Hardware and Software Design

Irvine, California, United States

Venue Start Date End Date
Irvine Marriott 10 Sep 2026, 10:00 AM PDT 10 Sep 2026, 2:00 PM PDT

Overview

This seminar provides an overview of MATLAB and Simulink workflows for modeling, simulation, verification, and system implementation targeting ASIC/FPGA and SoC. The agenda begins with a high-level introduction to model-based design followed by algorithm-to-implementation. Focused technical sessions will cover design verification and validation, synthesizable (RTL) HDL and C/C++ code generation for ARM based embedded systems.

Attendees will gain insight into how MathWorks tools can help streamline development from early algorithm exploration through hardware and software deployment.

Highlights

  • MATLAB and Simulink overview
  • Design Verification and Validation
  • HDL Code Generation and Optimization
  • C/C++ Code Generation for ARM Embedded Systems
  • Hardware/Software Co-Design

Who Should Attend

  • Design Verification (DV) Engineers
  • ASIC/FPGA Design Engineers
  • Embedded Software Engineers
  • Analog and Mixed Signal (AMS) Engineers
  • Digital Signal Processing (DSP) Engineers

About the Presenter

Mark Lin is an Advanced Application Engineer specializing in digital design verification workflows for ASIC and FPGA. Mark was a verification engineer at Broadcom for eight years, where he developed full-chip test environments. He earned a B.S. degree in electrical engineering from California State University of Los Angeles.

Robert Anderson is Principal Application Engineer at MathWorks, with a focus on HDL code generation and verification workflows for SoC, ASIC and FPGA.  Anderson started his career at AT&T Bell Laboratories and as a circuit designer. He then worked at Tellabs Operations as a circuit designer for high density echo-cancellation systems. These included linear cancellation, as well as acoustic cancellation. He also worked at Mentor Graphics, Xilinx, and AccelChip in technical marketing management and application engineering roles, where he specialized in high-level synthesis, optimization of ASIC and FPGA implementations, and MATLAB to HDL. Anderson received the Master’s degree from Northwestern University (2001) in electrical and computer engineering for communications and digital signal processing. 

Agenda

Time Title
10:00 am Registration and Welcome
10:30 am
  • MATLAB and Simulink Overview
  • Design Verification and Validation
  • Synthesizable (RTL) HDL Generation 
11:45 am Lunch 
12:15 pm
  • Optimized C/C++ Generation
  • System Integration 
1:15 pm Live Q&A

Product Focus

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