This submission has examples showing how to generate HDL Code from MATLAB code, Simulink models and Simscape models using HDL Coder.
About HDL Coder:
HDL Coder™ enables high-level design for FPGAs, SoCs, and ASICs by generating portable, synthesizable Verilog® and VHDL® code from MATLAB® functions, Simulink® models, and Stateflow® charts. You can use the generated HDL code for FPGA programming, ASIC prototyping, and production design.
HDL Coder automates prototyping generated code on Xilinx®, Intel®, and Microchip boards and generates IP cores for ASIC and FPGA workflows. You can optimize for speed and area, highlight critical paths, and generate resource utilization estimates before synthesis. HDL Coder provides traceability between Simulink models and generated Verilog and VHDL code, enabling code verification for high-integrity applications adhering to DO-254 and other standards.
인용 양식
Kiran Kintali (2025). HDLCoder Design Patterns and Examples (https://www.mathworks.com/matlabcentral/fileexchange/50098-hdlcoder-design-patterns-and-examples), MATLAB Central File Exchange. 검색 날짜: .
MATLAB 릴리스 호환 정보
개발 환경:
R2023a
R2012b 이하 모든 릴리스와 호환
플랫폼 호환성
Windows macOS Linux카테고리
- Code Generation >
- Code Generation > HDL Coder >
- FPGA, ASIC, and SoC Development > HDL Coder >
- FPGA, ASIC, and SoC Development >
Help Center 및 MATLAB Answers에서 Code Generation에 대해 자세히 알아보기
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버전 | 게시됨 | 릴리스 정보 | |
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3.0 | Updated MATLAB examples with R2023a release. Also attached new design pattern models with Simulink, Stateflow, MATLAB Function Blocks and Simscape. |
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2.0 | Significant improvements and several new examples. |
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1.1.0.1 | Updated license |
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1.1.0.0 | minor update: cleanup few mlint messages. |