Variable time delay for fixed-step discrete real value signals

The block implements a variable time delay, using interpolation to approximate substep delays.

The block implements a variable time-delay, or variable sample delay in discrete systems using fixed-step solver.
The output is interpolated, in order to approximate sub-sampletime delay. Therefore the input signal should be differentiable and should be able to obtain a wide range of numeric values (float, int, but not like bool).