hdlcoder std_logic_vector to stateflow type
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borzack 2020년 10월 14일
답변: Kiran Kintali 2020년 12월 22일
I've a following vhdl code
signal a : std_logic_vector(10 downto 0);
signal b : std_logic_vector(10 downto 0);
My goal is to rewrite in stateflow and reproduce it by hdlcoder.
is there an easy way to do it?
Aman Vyas 2020년 12월 22일
You can use Stateflow HDL Code generation workflow where you can try to restructure your logic in the form of Finite State Machines (FSM), notation diagram or state transition diagram.
You can use a chart to model a finite state machine or a complex control algorithm intended for realization as an ASIC or FPGA. When the model meets design requirements, you then generate HDL code (VHDL® or Verilog®) that implements the design embodied in the model. You can simulate and synthesize generated HDL code using industry standard tools, and then map your system designs into FPGAs and ASICs.
For more info you can refer the following link :
Hope it helps !
Kiran Kintali 2020년 12월 22일
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