how translate stateflow variable to hdl std_logic_vector(0 to 7)

조회 수: 1(최근 30일)
hdlcoder translate the stateflow variable fi(0,0,5,0) to std_logic_vector(0 downto 4), but sometimes I need std_logic_vector(0 to 4). Ofcourse if I use a boolean array hdlcoder translate it to std_logic_vector(0 to 4) but I can't use bitconcat, bitsliceget function, so in this case I need work with array while in the first case I work with bit.
is there a way to work with fi() type and set hdlcoder to translate big or little endian?

채택된 답변

Kiran Kintali
Kiran Kintali 2020년 10월 12일
HDLCoder does not currently support such customization. Fixed Point types generate DOWNTO syntax, and arrays including array of booleans generate TO syntax.
  댓글 수: 1
borzack 2020년 10월 12일
Ok thanks. Are there dedicate functions hdlcoder compatible to compare two boolean array?
if A==B ... end

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추가 답변(1개)

Kiran Kintali
Kiran Kintali 2020년 10월 12일
>> type compBoolVector.m
function y = compBoolVector(u, v)
y = all(u == v);
>> a = true(1, 10); b = a; % create some example types
>> codegen -config:hdl -args{a, b} compBoolVector
>> c = coder.config('hdl');
>> codegen -config c -args {a, b} compBoolVector
### Begin VHDL Code Generation
### Generating HDL Conformance Report compBoolVector_hdl_conformance_report.html.
### HDL Conformance check complete with 0 errors, 0 warnings, and 0 messages.
### Working on compBoolVector as compBoolVector.vhd.
### Generating Resource Utilization Report resource_report.html.
Code generation successful.

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