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HDL Coder Sharing alters wordlength of multiplier

조회 수: 2 (최근 30일)
Manuel K
Manuel K 2020년 9월 28일
댓글: Kiran Kintali 2020년 11월 20일
I've recognized that my design uses way too much DSP-Slices than it should, so I looked at the generated model in detail and also the corresponding vhdl-files. To my surprise I found that the wordlength of the multipliers was twice (from 32 to 64) as originally specified. This happens regardless of whether the wordlength/datatype is inherited or specified. Why does this happen and is there a way to suppress this behavior?
The input fixed-point data types have the same wordlength and do not change in the generated model or code.

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Kiran Kintali
Kiran Kintali 2020년 9월 29일
In hardware multipliying two inputs of size 'n' and 'm' would result in full precision output of 'n+m'. The result is further truncated with output type as specified in the multiplier block. Is there a way to reduce input word lengths to reduce requirements on size of the multiplier needed to perform the computation?
For additional assistance, please share a multiplier block model with necessary options set to further diagnose the problem.
  댓글 수: 2
Manuel K
Manuel K 2020년 10월 2일
Thanks for your help and clarification.
So there is no way to reduce the size to something smaller than 'n+m'?
If this is the intended behavoir, it should be explained under the help-menu of the multiplier block. Otherwise I think it is a bit unintuitive, that it always keeps the full precision.
Kiran Kintali
Kiran Kintali 2020년 11월 20일
If I understand correctly you are looking to optimize the multiplier size. This can be done using wide variety of range analysis features in Fixed Point Designer product.
You can do range analysis (using testbench simulation or deriving ranges statically based on input types and type propagation). This can be done as a pre-step to HDL code generation, optimize types, apply new input wordlengths to your design.
Once the fixed point input type sizes are chosen HDL Coder always uses the n+m rule to give you correct hardware behavior in the generated HDL.

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