HDL Coder Flatten Hierachy does not work with masked library block

조회 수: 2 (최근 30일)
Manuel K
Manuel K . 2020년 8월 3일
댓글: Manuel K . 2020년 8월 29일
In order to balance (delays, pipelining) my feedback-loops, a subsystem with "Flatten Hierachy" enabled is positioned above the blocks of the feedback-loop. Because this will make the generated model very messy, another "normal" subsystem is inserted above. This works fine and makes the generated model readable.
The Problem appears, when I convert this whole set to a custom library block. Whenever the mask of the library-block contains some parameter (under Parameters & Dialog) or anything under Documentation, the model won't compile and the error I get complains about not beeing able to balance the feedback-loop. Even dummy-parameters cause an error, although they are invisible, disabled and don't get evaluated.
This causes the following issues:
  • The sublibrary containing the block does not appeare correctly inside the library browser (drop-down-arrow).
  • I can not use parameters with the library block.
Is there a reason for this behavior?
  댓글 수: 1
Manuel K
Manuel K 2020년 8월 29일
I just want to add that masking a subsystem (with parameters or documentation) also affects other settings like "streaming" and "sharing". In order to let the Workflow Advisor apply these principles correctly I yet again had to delete the masking or at least the "parameters" and "documentation" section.
By "streaming and sharing correctly" I mean that no new base model-rate gets produced if not needed. Why is there not at least a warning, when your generated model requires a faster clock-rate than you specified e.g. in the Target Frequency section? There is missing a feature to control this behavior: when a subsystem gets sampled at a sample rate f_s1 < than clock rate f_clk, the latency introduced by "sharing" or "streaming" is no problem (when clock-rate pipelining gets applied). But sometimes HDL coder will nevertheless introduce a new rate f_s2 locally which will be faster than the sample rate f_s1 by the specified streaming or sharing factor which can cause the problem that this cannot be done with the clock rate f_clk of the model because it is not an integer multiple. Therefore HDL Coder just introduces a new higher clock_rate which just ignores your hardware-specification.

댓글을 달려면 로그인하십시오.

답변 (1개)

Kiran Kintali
Kiran Kintali 2020년 8월 4일
Will you be able to provide a model with reproduction steps?
I suspect this is related to failure to do delay balancing due to feedback loop and not related to FlattenHierarchy. If that is the case either eliminating the need for delay balancing the feedback loop or using ClockRatePipelining would be your two options.
Reproduction model can help in providing better workaround if any.
  댓글 수: 1
Manuel K
Manuel K 2020년 8월 4일
편집: Manuel K 님. 2020년 8월 4일
I'll upload a simplified model tomorrow, however the delay balancing and pipeling both work fine and only throw an error, when the subsystem above the subsystem with the option "Flatten Hierarchy" set, has a mask with parameters.
My structure from top to bottom looks like this:
1: masked subsystem which should become the library block (only when it has parameters or a documentation, the error appears)
2: subsystem with option "Flatten Hierarchy" set
3: blocks that form a feedback loop

댓글을 달려면 로그인하십시오.




Community Treasure Hunt

Find the treasures in MATLAB Central and discover how the community can help you!

Start Hunting!

Translated by