I used fdatool to create VHDL of a lowpass fir filter with Fpass 1KHz and and Fstop 2KHz with sampling freq 20kHz.
I have a 12 bit ADC/DAC with a range from about -1.5V to 1.5V or -2048 to 2048 in signed binary. When I quantize the filter should I make the fraction length 0 so I get the +-2048 range or 10 so I get a range of +- 4V?
I am using a function generator for the input to the ADC.

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Abhishek Gupte
Abhishek Gupte 2012년 1월 11일

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When you select the 'Set quantization parameters' tool in FDATOOL, in the 'Coefficients' tab, I would recommend checking the 'Best precision fractional length' checkbox. In the 'Input/Output' tab, you can set the 'Input range' to 1.5 V. I think that letting FDATOOL compute the best fractional length is the right way to go.

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Mark
Mark 2012년 1월 17일
Thanks Abhishek,
I checked 'Best precision fractional length' for the Coefficients tab and I set my input and output range to +- 1.5V. After synthesizing and programming my spartan 3E. I got a very noisy signal.
It turns out that my filter clock frequency was 100 MHz while the sampling frequency in the FDATOOL was set to 20 kHz. I changed the 100 MHz clock to 20 kHz and now my filter works.

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