How to initialize Xilinx UltraRAMs?

조회 수: 8 (최근 30일)
Charles . 2023년 3월 22일
답변: Charles . 2023년 3월 27일
I'd like to use UltraRAMs to store what are essentially filter coefficients (there's about 20 K values, 26 bits of precision). Right now, I use the Simple Dual Port RAM System and initialize it from a vector in the Matlab workspace. This shows up in Verilog as 64K lines of initialization.
My understanding of UltraRAMs is that you can't initialize them to an arbitrary set of values - they don't work the same as BlockRAMs. Vivado seems to be ignoring the "ultra" RAMDirective for this usage, and that's the only explanation I can think of.
Is there a way around this? I'm thinking of something where I have to "manually" write the initialization in the module where the RAM is located, and have it run on startup, but which seems fraught with complications. BlockRAMs work perfectly fine, but I have lots of UltraRAMs, and since BlockRAMs are more flexible, I want to save them for other parts of the system that need that flexibility.

답변 (2개)

Ryan Baird
Ryan Baird 2023년 3월 23일
My understanding is that you're correct, and that there's no easy way around it. Since the hardware doesn't support initializing UltraRAM to an arbitrary set of values, you have to do it manually by writing to the RAM.

Charles 2023년 3월 27일
Ok, I figured out a way around this:
  • I provide some ports at the top level system to access the memory; these will be the data in, write enable, write address and an address source bit to select between the write address and the normal-operation read address
  • Our Verilog guy will manage this on system startup, writing the coefficients through the above interface
  • In simulation, I initialize the RAM in the usual way, through a Matlab variable. When time comes to run HDL Coder, this variable is set to 0 (zero), so that when Vivado synthesizes, it obeys the ultra RAMDirective
This works.




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