HDL Counter with programmable limit
조회 수: 8 (최근 30일)
I am using Simulink/HDL Coder to design a system. I use the HDL Counter block a lot. As I learn more, I realize that the HDL Counter doesn't quite do everything I need.
In particular, I'd like to be able to programmatically set the "Count to" value (for a Count limited counter) depending on the system configuration. For example: say I have a signal vector that is Nsamples long. Depending on the system configuration, Nsamples could be 1000 or it could be 1500 or any arbitrary value in that range. My system needs to count out those samples and do processing that depends on the length. But since the counter limit is set via a mask parameter, it gets compiled in as a constant and cannot be changed at runtime. The generated HDL code shows that this is a constant compiled into the source, hence not at all easily settable.
I would be happy if this could be set once on startup from a register - the counter limit would never need to change again, and a system reconfig would always involve a reset/reload of the FPGA. To change the value with the current HDL Counter, I will need to change it in the design and resynthesize the whole system, not to mention test it to make sure it still works. Is there some other block out there I'm missing? Or, should I go and design my own?
Suggestions welcome. Thanks,