Vision
R2026bYou can use SoC Blockset™ Support Package for AMD FPGA and SoC Devices to model and simulate video processing algorithms such as histogram equalization. Simulate your algorithm with SoC components such as DDR memory, software tasks, and AXI interfaces. You can then take additional steps to deploy your design on an SoC device.
Workflow Overview
Categories
- Develop Algorithms with Live Video Capture
Develop frame-based or pixel-streaming algorithms that operate on live camera data from your hardware
- Implement on Hardware
Prototype vision algorithms on Zynq SoC devices
- Deep Learning
Integrate deep learning processors with video streaming designs
Featured Examples
Edge Detection and Image Overlay
Implement an edge detection and image overlay system with HDMI input and output.
Histogram Equalization Using Video Frame Buffer
Perform histogram equalization with HDMI input and output and using external memory for video frame buffering.
Vertical Video Flipping Using External Memory
Flip an incoming video stream vertically by using a random-access external memory interface.
Contrast Limited Adaptive Histogram Equalization with External Memory
Implement the contrast-limited adaptive histogram equalization (CLAHE) algorithm for FPGA, including an external memory interface.
Deploy and Verify YOLO Object Detector Postprocessing on FPGA
Deploy a you-only-look-once (YOLO) object detector with preprocessing, deep learning (DL) IP, and postprocessing on an FPGA, and verify the design.
Corner Detection with Zynq-Based Hardware and MIPI Sensor
Target a corner detection algorithm to a ZCU106 device with a MIPI® add-on card by using the SoC Blockset™ Support Package for AMD® FPGA and SoC Devices.
MultiPixel-MultiComponent Streaming with Zynq-Based Hardware
Target multipixel multicomponent algorithm to the Zynq® hardware using the SoC Blockset™ Support Package for AMD® FPGA and SoC Devices.
Generate IP Core with AXI4-Stream Video Interface
Use the AXI4-Stream Video interface to enable high speed video streaming on the generated HDL IP core.
Generate IP Core from Frame-Based Model with AXI4 Stream Video Interface
You can use the HDL Coder™ frame-to-sample optimization to design and deploy frame-based algorithms that use AXI4-Stream Video interfaces to enable high-speed video streaming.
Deploy a Real-Time Video Frame Accumulator by Using External Memory
Build a frame accumulator on Zynq using frame‑to‑sample optimization for real‑time streaming.
