AD9361 Tx

Connect hardware logic to AD9361-based Zynq transmitter

Add-On Required: This feature requires the SoC Blockset Support Package for Xilinx Devices add-on.

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Libraries:
SoC Blockset Support Package for Xilinx Devices / MPSoC / ZCU102
SoC Blockset Support Package for Xilinx Devices / Zynq-7000 / ZC706
SoC Blockset Support Package for Xilinx Devices / Zynq-7000 / ZedBoard

Description

The AD9361 Tx block connects your hardware logic to the AD9361 transmitter hardware. In simulation, this block returns data to a file or output port. It does not connect to the radio hardware from simulation.

The block supports up to two channels to send data.

Examples

Packet-Based ADS-B Transceiver

Packet-based systems are common in wireless communications. Data is received over the air and is decoded as discrete packet data on a compute device. For given system requirements, it is difficult to design a system and implement directly on SoC as it often involves long iterations of debugging and integration on hardware since hardware effects are difficult to account for at design time. In this example, you will design packet-based airplane tracking application based on Automatic Dependent Surveillance Broadcast (ADS-B) standard, partitioned between FPGA and embedded processor. Unlike traditional methods, you will simulate the application design with memory interface before implementation on hardware using SoC Blockset™ to shorten development time. You will then validate the design on hardware by automatically generated code from the model.

Open Script

Transmit and Receive Tones Using AD9361 Dual-Channels

Design, simulate, and deploy dual-channel application system with AD9361 RF card using SoC Blockset™ on Xilinx^® Zynq^® UltraScale+™ MPSoC ZCU102 Evaluation Kit.

Open Script

Limitations

• In the hardware setup, set Hardware Board to one of the supported Xilinx boards. You can find the supported boards in the Libraries list at the top of this page. Set Add-on Card to None.

• This block supports SoC generation using the SoC Builder tool. This block does not support the IP core generation workflow. For more information on workflows, see SoC Generation Workflows.

Ports

Input

txDataIn — Transmit data

complex matrix

Transmit data, specified as a complex matrix. The number of columns in the matrix depends on the number of channels in use. Each column corresponds to a channel of complex data sent via one channel. In single-channel mode, the number of elements in a column must be even.

This port supports complex values with these data types:

• 16-bit signed integers — Since the AD9361 RF chip has a 12-bit DAC, only the 12 most significant bits of the I and Q samples are used.

• Single-precision floating point — Complex values in the range of [–1, 1]. Since the AD9361 RF chip has a 12-bit DAC, numbers of magnitude less than 0.0625 are lost.

• Double-precision floating point — Complex values in the range of [–1, 1]. Since the AD9361 RF chip has a 12-bit DAC, numbers of magnitude less than 0.0625 are lost.

Data Types: int16 | single | double
Complex Number Support: Yes

txValid — Validity of transmit data

Boolean scalar

Validity of the transmit data, specified as a Boolean scalar. When txValid is 1, the block captures the input data from the txDataIn port. When txValid is 0, the block considers the input data as invalid and does not capture it.

Output

txDataOut — Transmit data

complex matrix

Transmit data passed through the block, returned as a complex matrix. The number of columns in the matrix depends on the number of channels in use. Each column corresponds to a channel of complex data received on one channel.

This port supports complex values with these data types:

• 16-bit signed integers — Since the AD9361 RF chip has a 12-bit DAC, only the 12 most significant bits of the I and Q samples are used.

• Single-precision floating point — Complex values in the range of [–1, 1]. Since the AD9361 RF chip has a 12-bit DAC, numbers of magnitude less than 0.0625 are lost.

• Double-precision floating point — Complex values in the range of [–1, 1]. Since the AD9361 RF chip has a 12-bit DAC, numbers of magnitude less than 0.0625 are lost.

Dependencies

To enable this port, set the Send simulation input to parameter to Output port.

Data Types: int16 | single | double
Complex Number Support: Yes

Parameters

Enable channel 1 — Option to enable channel 1

on (default) | off

Select this parameter to enable the transmit channel 1.

Enable channel 2 — Option to enable channel 2

off (default) | on

Select this parameter to enable the transmit channel 2.

Send simulation input to — Simulation behavior

Data file (default) | Output port | Terminator

Simulation behavior, specified as one of these values:

• Data file –– Export valid data from the txDataIn port to a file, using the Dataset name and Source name parameters.

• Output port –– Pass through data from input port.

• Terminator –– Connect the txValidIn port to a terminator inside the block.

Dataset name — Name of recorded file

rf_tx_data.tgz (default) | file path

Name of recorded file, specified as a file path on the host computer or browse and select the file on the host computer. This block supports only TGZ files created using the SoC Blockset data recording API. The default value is the dataset recorded from the Packet-Based ADS-B Transceiver example.

Source name — Name of dataset

RF data Ch-1 (default) | character vector

Name of a dataset available within the recorded dataset file, specified as a character vector. The dataset must exist in the file specified in the Dataset name parameter. You can either type the name in the Source name box or click Select to view a list of sources available in the recorded data file and examine their properties. The default value is the dataset recorded from the Packet-Based ADS-B Transceiver example.

Extended Capabilities

HDL Code Generation

Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

To automatically generate HDL code for your design, and execute on an SoC device, use the SoC Builder tool.

Version History

Introduced in R2019a

R2024a: Dual channels support

The block now supports two transmit channels. You can enable dual channels by selecting the Enable channel 1 and Enable channel 2 parameters from the block mask.