Reduce Model Complexity
Simulink® Design Verifier™ software works most effectively at analyzing large models using a bottom-up approach. In this approach, the software analyzes smaller model components first, which can be faster than using the default settings. A bottom-up approach offers several advantages:
It allows you to solve the problems that slow down error detection, test generation, or property proving in a controlled environment.
Solving problems with small model components before analyzing the model as a whole is more efficient, especially if you have unreachable components in your model that you can only discover in the context of the model.
You can debug more quickly, finding and fixing problems iteratively.
If a singular model component has a problem—for example, a component is unreachable in simulation—it can prevent the software from generating tests for all the objectives in a large model.
If you want to work around compatibility limitations in your model or customize model elements for analysis, you can use Simulink Design Verifier block replacement rules. If you want to generate additional values for parameters in your model during analysis, use Simulink Design Verifier parameter configurations.
|Replace blocks for analysis|
Reduce Model Complexity
- Bottom-Up Approach to Model Analysis
Explains the benefits of analyzing a model starting with low-level elements.
- Sources of Model Complexity
Describes model characteristics that may complicate an analysis.
- Role of Approximations During Model Analysis
Approximations Simulink Design Verifier performs before beginning its analysis.
- Logical Operations
If you have a Simulink model with both logical and arithmetic operations, consider analyzing only the logical operations.
- Model Blocks
Analyzing Model blocks that reference external models.
- Extract Subsystems for Analysis
Explains how subsystems and atomic subcharts are extracted for individual analysis.
- Manage Model Data to Simplify the Analysis
Simplify your model to simplify the Simulink Design Verifier analysis.
- Partition Model Inputs for Incremental Test Generation
As described in Constrain Data, you can constrain the values of model inputs using the Simulink Design Verifier Test Condition block.
- Analyzing Models with Large Verification State Space
Techniques to simplify the complexity of models with large verification state spaces.
- Block Reduction
Explains how Simulink reduces blocks during simulation and how it affects the Simulink Design Verifier analysis.
Perform Block Replacement
- What Is Block Replacement?
Brief overview of block replacements.
- Built-In Block Replacements
Describes the factory default block replacement rules and library.
- Template for Block Replacement Rules
Introduces a template for creating custom block replacement rules.
- Block Replacements for Unsupported Blocks
This example shows how to use Simulink® Design Verifier™ functions to replace unsupported blocks and how to customize test vector generation for specific requirements.