논리
R2026bCMOS AND, CMOS OR, CMOS NOT과 같은 집적 회로용 논리 게이트
부울 함수를 구현하는 논리 게이트를 결합하여 단일 논리 출력을 생성합니다.
Simscape 블록
![]() | CMOS AND | Behavioral model of CMOS AND gate |
![]() | CMOS Buffer | Behavioral model of CMOS Buffer gate |
![]() | CMOS NAND | Behavioral model of CMOS NAND gate |
![]() | CMOS NOR | Behavioral model of CMOS NOR gate |
![]() | CMOS NOT | Behavioral model of CMOS NOT gate |
![]() | CMOS OR | Behavioral model of CMOS OR gate |
![]() | CMOS XOR | Behavioral model of CMOS XOR gate |
![]() | D Flip-Flop | Behavioral model of D flip-flop (R2024a 이후) |
![]() | D Latch | Behavioral model of D latch (R2024a 이후) |
![]() | S-R Latch | Behavioral model of S-R Latch |
![]() | Schmitt Trigger | Behavioral model of Schmitt trigger |
도움말 항목
- Parameterize Blocks from Data Sheets
Overview of techniques used to specify block parameters to match the data from manufacturer data sheets.
- Selecting the Output Model for Logic Blocks
Explore the two output models available for logic blocks.
- Plot Basic Input-Output Voltage Characteristics of Logic Gates
Plot basic input-output voltage characteristics of logic gates based on block parameter values.










