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Decision feedback equalizer (DFE) with clock and data recovery (CDR)

**Library:**SerDes Toolbox / Datapath Blocks

The DFECDR block adaptively processes a sample-by-sample input signal or analytically processes an impulse response vector input signal to remove distortions at post cursor taps.

The DFE modifies baseband signals to minimize the intersymbol interference (ISI) at the clock sampling times. The DFE samples data at each clock sample time and adjusts the amplitude of the waveform by a correction voltage.

For impulse response processing, the hula-hoop algorithm is used to find the clock
sampling locations. The zero-forcing algorithm is then used to determine the
*N* correction factors necessary to have no ISI at the *N*
subsequent sampling locations, where *N* is the number of DFE taps.

For sample-by-sample processing, the clock recovery is accomplished by a first order phase
tracking model. The bang-bang phase detector utilizes the unequalized edge samples and
equalized data samples to determine the optimum sampling location. The DFE correction voltage
for the *N*-th tap is adaptively found by finding a voltage that compensates
for any correlation between two data samples spaced by *N* symbol times. This
requires a data pattern that is uncorrelated with the channel ISI for correct adaptive
behavior.