IIR Filter

Implement infinite impulse response (IIR) filter

Since R2020a

• 

Libraries:
Motor Control Blockset / Signal Management
Motor Control Blockset HDL Support / Signal Management

Description

The IIR Filter block implements a discrete first-order infinite impulse response (IIR) filter on the specified input signal. The block supports fixed-point and floating-point data types. The block is also optimized for code generation when used with the model settings and configuration adopted by the examples shipped in Motor Control Blockset™.

We recommend that you use fixed-step discrete solver for this block to enable code generation and ensure accurate simulation.

Equations

You can configure the IIR filter by using the filter coefficient ($$a$$) block parameter to set the required cutoff frequency (f_c) for the filter.

This equation describes computation of the filter coefficient from the cutoff frequency:

$a= \left( \frac{2\pi T_s{f}_c}{2\pi T_s{f}_c+1} \right)$

Alternatively, the block also computes the theoretical cutoff frequency for the given sample time using a filter coefficient:

$f_c= \left( \frac{a}{(1-a)\cdot 2\pi \cdot T_s} \right)$

Use the Filter type parameter to configure the block either as a low-pass or high-pass filter.

Low-pass filter:

$$y\left(k\right)=a\cdot x\left(k\right)+(1-a)\cdot y\left(k-1\right)$$

High-pass filter:

$$y\left(k\right)=(1-a)\cdot x\left(k\right)- (1-a)\cdot x\left(k-1\right)+(1-a)\cdot y\left(k-1\right)$$

where:

• f_c is the cutoff frequency of the IIR filter.

• $$a$$ is the filter coefficient in the range (0, 1].

• $y\left(k\right)$ is the filtered output value at time sample $$k$$.

• $y\left(k-1\right)$ is the filtered output value at time sample $k-1$.

• $x\left(k\right)$ is the sampled input value at time sample $$k$$.

• $x\left(k-1\right)$ is the filtered output value at time sample $k-1$.

• T_s is the sample time of the IIR Filter block.

Ports

Input

x — Sampled input signal

scalar

Sampled values of the raw input signal in the time domain.

Data Types: single | double | fixed point

Output

y — Filtered output signal

scalar

Filtered output signal returned by the IIR Filter block in the time domain.

Data Types: single | double | fixed point

Parameters

Filter type — IIR filter type

Low-pass (default) | High-pass

Type of the IIR filter.

Filter co-efficient — Filter coefficient of IIR filter

0.01 (default) | scalar in the range (0,1]

Filter coefficient of the IIR filter. The data type of this parameter is the same as that of the input signal. We suggest that you check the precision of the parameter value in this data type.

Display cutoff frequency — Display the cutoff frequency parameters

off (default) | on

Select this parameter for the block to display the Discrete step size (s) and Theoretical cutoff frequency (Hz) parameters.

Discrete step size (s) — Sample time after which block executes again

50e-6 (default) | scalar

The fixed time interval (in seconds) between every two consecutive instances of block execution.

Dependencies

To display this parameter, select the Display cutoff frequency parameter.

Theoretical cutoff frequency (Hz) — Theoretical cutoff frequency of IIR filter

32.1525 | scalar

Theoretical cutoff frequency (in Hertz) of the IIR filter. This parameter is not configurable.

Dependencies

To display this parameter, select the Display cutoff frequency parameter.

Extended Capabilities

C/C++ Code Generation
Generate C and C++ code using Simulink® Coder™.

HDL Code Generation

Generate VHDL, Verilog and SystemVerilog code for FPGA and ASIC designs using HDL Coder™.

HDL Coder™ provides additional configuration options that affect HDL implementation and synthesized logic.

HDL Architecture

This block has one default HDL architecture.

HDL Block Properties

ConstrainedOutputPipeline	Number of registers to place at the outputs by moving existing delays within your design. Distributed pipelining does not redistribute these registers. The default is 0. For more details, see ConstrainedOutputPipeline (HDL Coder).
InputPipeline	Number of input pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see InputPipeline (HDL Coder).
OutputPipeline	Number of output pipeline stages to insert in the generated code. Distributed pipelining and constrained output pipelining can move these registers. The default is 0. For more details, see OutputPipeline (HDL Coder).

Fixed-Point Conversion
Design and simulate fixed-point systems using Fixed-Point Designer™.

Version History

Introduced in R2020a