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Verify Viterbi Decoder Using HDL Cosimulation

This example shows how to use HDL Verifier™ in conjunction with Mentor Graphics ModelSim®/QuestaSim® or Cadence Incisive®/Xcelium® to verify HDL code for a fixed-point Viterbi decoder.

Open the Simulink Model

Launch HDL Simulator

Before launching the HDL simulator, make sure the executables are on the MATLAB® system path. Launch the simulator by double-clicking the Startup Command block.

Run Simulation

When HDL simulator has finished compiling the VHDL files and loading the simulation, the text "Ready for cosimulation ..." is displayed in the HDL simulator command window. After you see this text, start Simulink simulation from the open model.

When the simulation stops, observe the bit error rate displayed at the "BER Display" block.

Rerun Simulation with Different Parameters.

There are two parameters that control the behavior of this model. The first is the frame size and the other is the Es/No used for simulation. You can change those parameters in the MATLAB console. For example,

FrameSize = 10;
EsNo      = 5;

Then you can rerun the cosimulation with updated parameters by starting the simulation again from the model.

Finish Simulation

Close the HDL simulator session. Then return to Simulink and close the model.