HDL Verifier™ provides two types of test benches that generate a C-language component and integrate it into a SystemVerilog test bench with a direct programming interface (DPI). One test bench verifies a generated C component against saved data vectors from your Simulink® subsystem. The other test bench verifies generated HDL code against a C component generated from the entire Simulink model.
Component Test Bench — When you generate a C component from a Simulink subsystem for use as a DPI component, you can optionally generate a SystemVerilog test bench. The test bench verifies the generated DPI component against data vectors from your Simulink model. This feature is available in the Model Configuration Parameters dialog box, under Code Generation. See Generate SystemVerilog DPI Component.
HDL Code Test Bench — When you generate HDL code from a subsystem,
using HDL Coder™, you can optionally generate a SystemVerilog test bench. This test
bench compares the output of the HDL implementation against the results of the
Simulink model. You can access this feature in HDL Workflow Advisor under HDL Code Generation > Set Testbench Options, or in the Model Configuration Parameters dialog box, under HDL Code Generation > Test Bench. Alternatively, for command-line access, set the
GenerateSVDPITestBench property of
makehdltb. See Verify HDL Design With Large Data Set Using SystemVerilog DPI Test Bench (HDL Coder).
Both types of test benches require a Simulink Coder™ license.
HDL Verifier converts matrices and vectors to one-dimensional arrays in SystemVerilog. For example, a 4-by-2 matrix in Simulink is converted to a one-dimensional array of eight elements in SystemVerilog.
These subsystems do not support DPI test bench generation:
Subsystem with action port
The SystemVerilog DPI component generator also creates a test bench. You can use this test bench to verify that the generated SystemVerilog component is functionally equivalent to the original Simulink subsystem. The test bench saves data vectors from your Simulink simulation to apply as stimuli and to check against the output of the component. This test bench is not intended as a replacement for a system test bench for your own application. However, you can use the generated test bench as a starting example for your own system test bench.
If you enable logging on test points in your model, the generated test bench also compares their signal values in the SystemVerilog component with logged values from Simulink.
HDL Verifier does not support test bench generation for custom generated SystemVerilog code. See Customization.
When your subsystem contains signals with more than one sample rate, the generated test bench includes a timing controller module. The timing controller generates input clock signals at the appropriate rates. Input stimuli and expected data outputs are applied and checked according to their sample rates.
When you generate HDL code from a subsystem, using HDL Coder, you can also generate a SystemVerilog DPI test bench. This test bench compares the output of the HDL implementation against the results of the Simulink model. In addition to C code for your DUT subsystem, the coder also generates C code for the portion of your model that generates the input stimuli. Generation of this test bench is faster than the default HDL test bench for large data sets. This advantage is because the coder does not run the Simulink model to obtain the input and output data vectors. The generated C component calculates input stimuli and the output results for comparison with the HDL implementation.
The generated SystemVerilog test bench includes:
Generated Verilog® or VHDL® code for your subsystem
Generated C component
Code to compare the output of the HDL code with the output of the C component.
Run this test bench to verify the generated HDL code implements the same algorithm as your Simulink model.