uvmbuild

Generate UVM test bench from Simulink model

Description

example

uvmbuild(dut,sequence,scoreboard) generates a SystemVerilog top module, which includes a Universal Verification Methodology (UVM) test bench and a behavioral design under test (DUT). The UVM test bench includes a sequence, a scoreboard, monitors, and drivers. The uvmbuild function maps:

  • The Simulink® DUT subsystem to a generated SystemVerilog DPI behavioral DUT

  • The Simulink sequence subsystem to a UVM sequence block

  • The Simulink scoreboard subsystem to a UVM scoreboard

Examples

collapse all

Simulink Model Structure

This example uses a Simulink® model, that includes these three subsystems.

  • A sequence subsystem, which generates stimulus for the DUT.

  • A DUT subsystem, which represents your HDL design.

  • A scoreboard subsystem, which collects the outputs and checks them. In this example the DUT is a simple delay block.

open_system('hdlv_uvmbuild');

Generate UVM Test Bench

Generate a UVM test bench from this Simulink model, specifying the paths to the DUT, sequence, and scoreboard subsystems.

uvmbuild('hdlv_uvmbuild/DUT','hdlv_uvmbuild/Sequence','hdlv_uvmbuild/Scoreboard');
### Starting DPI subsystem generation for UVM test bench
### Starting build procedure for model: DUT
### Starting SystemVerilog DPI Component Generation
### Generating DPI H Wrapper /tmp/Bdoc19b_1192687_66220/tp14c8ac48/ex87636604/DUT_build/DUT_dpi.h
### Generating DPI C Wrapper /tmp/Bdoc19b_1192687_66220/tp14c8ac48/ex87636604/DUT_build/DUT_dpi.c
### Generating UVM module package /tmp/Bdoc19b_1192687_66220/tp14c8ac48/ex87636604/DUT_build/DUT_dpi_pkg.sv
### Generating SystemVerilog module /tmp/Bdoc19b_1192687_66220/tp14c8ac48/ex87636604/DUT_build/DUT_dpi.sv
### Generating makefiles for: DUT_dpi
### Invoking make to build the DPI Shared Library
### Successful completion of build procedure for model: DUT
### Starting build procedure for model: Sequence
### Starting SystemVerilog DPI Component Generation
### Generating DPI H Wrapper /tmp/Bdoc19b_1192687_66220/tp14c8ac48/ex87636604/Sequence_build/Sequence_dpi.h
### Generating DPI C Wrapper /tmp/Bdoc19b_1192687_66220/tp14c8ac48/ex87636604/Sequence_build/Sequence_dpi.c
### Generating UVM module package /tmp/Bdoc19b_1192687_66220/tp14c8ac48/ex87636604/Sequence_build/Sequence_dpi_pkg.sv
### Generating SystemVerilog module /tmp/Bdoc19b_1192687_66220/tp14c8ac48/ex87636604/Sequence_build/Sequence_dpi.sv
### Generating makefiles for: Sequence_dpi
### Invoking make to build the DPI Shared Library
### Successful completion of build procedure for model: Sequence
### Starting build procedure for model: Scoreboard
### Starting SystemVerilog DPI Component Generation
### Generating DPI H Wrapper /tmp/Bdoc19b_1192687_66220/tp14c8ac48/ex87636604/Scoreboard_build/Scoreboard_dpi.h
### Generating DPI C Wrapper /tmp/Bdoc19b_1192687_66220/tp14c8ac48/ex87636604/Scoreboard_build/Scoreboard_dpi.c
### Generating UVM module package /tmp/Bdoc19b_1192687_66220/tp14c8ac48/ex87636604/Scoreboard_build/Scoreboard_dpi_pkg.sv
### Generating SystemVerilog module /tmp/Bdoc19b_1192687_66220/tp14c8ac48/ex87636604/Scoreboard_build/Scoreboard_dpi.sv
### Generating makefiles for: Scoreboard_dpi
### Invoking make to build the DPI Shared Library
### Successful completion of build procedure for model: Scoreboard
### Starting UVM test bench generation for model: hdlv_uvmbuild
### Generating UVM transaction object /tmp/Bdoc19b_1192687_66220/tp14c8ac48/ex87636604/hdlv_uvmbuild_uvmbuild/uvm_testbench/uvm_artifacts/mw_DUT_trans.sv
### Generating UVM interface /tmp/Bdoc19b_1192687_66220/tp14c8ac48/ex87636604/hdlv_uvmbuild_uvmbuild/uvm_testbench/uvm_artifacts/mw_DUT_if.sv
### Generating UVM sequence /tmp/Bdoc19b_1192687_66220/tp14c8ac48/ex87636604/hdlv_uvmbuild_uvmbuild/uvm_testbench/sequence/mw_DUT_sequence.sv
### Generating UVM sequence transaction /tmp/Bdoc19b_1192687_66220/tp14c8ac48/ex87636604/hdlv_uvmbuild_uvmbuild/uvm_testbench/sequence/mw_DUT_sequence_trans.sv
### Generating UVM driver /tmp/Bdoc19b_1192687_66220/tp14c8ac48/ex87636604/hdlv_uvmbuild_uvmbuild/uvm_testbench/uvm_artifacts/mw_DUT_driver.sv
### Generating UVM monitor /tmp/Bdoc19b_1192687_66220/tp14c8ac48/ex87636604/hdlv_uvmbuild_uvmbuild/uvm_testbench/uvm_artifacts/mw_DUT_monitor.sv
### Generating UVM agent /tmp/Bdoc19b_1192687_66220/tp14c8ac48/ex87636604/hdlv_uvmbuild_uvmbuild/uvm_testbench/uvm_artifacts/mw_DUT_agent.sv
### Generating UVM scoreboard /tmp/Bdoc19b_1192687_66220/tp14c8ac48/ex87636604/hdlv_uvmbuild_uvmbuild/uvm_testbench/scoreboard/mw_DUT_scoreboard.sv
### Generating UVM environment /tmp/Bdoc19b_1192687_66220/tp14c8ac48/ex87636604/hdlv_uvmbuild_uvmbuild/uvm_testbench/uvm_artifacts/mw_DUT_environment.sv
### Generating UVM test /tmp/Bdoc19b_1192687_66220/tp14c8ac48/ex87636604/hdlv_uvmbuild_uvmbuild/uvm_testbench/uvm_artifacts/mw_DUT_test.sv
### Generating UVM top /tmp/Bdoc19b_1192687_66220/tp14c8ac48/ex87636604/hdlv_uvmbuild_uvmbuild/uvm_testbench/top/mw_DUT_top.sv
### Generating UVM test package /tmp/Bdoc19b_1192687_66220/tp14c8ac48/ex87636604/hdlv_uvmbuild_uvmbuild/uvm_testbench/top/hdlv_uvmbuild_pkg.sv
### Generating UVM test bench simulation script for Mentor Graphics QuestaSim/Modelsim /tmp/Bdoc19b_1192687_66220/tp14c8ac48/ex87636604/hdlv_uvmbuild_uvmbuild/uvm_testbench/top/run_tb_mq.do
### Generating UVM test bench simulation script for Cadence Incisive /tmp/Bdoc19b_1192687_66220/tp14c8ac48/ex87636604/hdlv_uvmbuild_uvmbuild/uvm_testbench/top/run_tb_incisive.sh
### Generating UVM test bench simulation script for Cadence Xcelium /tmp/Bdoc19b_1192687_66220/tp14c8ac48/ex87636604/hdlv_uvmbuild_uvmbuild/uvm_testbench/top/run_tb_xcelium.sh
### Generating UVM test bench simulation script for Synopsys VCS /tmp/Bdoc19b_1192687_66220/tp14c8ac48/ex87636604/hdlv_uvmbuild_uvmbuild/uvm_testbench/top/run_tb_vcs.sh

Observe Generated Output

The uvmbuild function creates a directory named hdlv_uvmbuild_uvmbuild containing the uvm_testbench directory. The uvm_testbench directory includes these subdirectories.

  • The top directory includes a SystemVerilog top module and generated scripts to execute in your HDL simulation environment.

  • The DPI_dut directory contains the SystemVerilog-DPI behavioral DUT.

  • The sequence directory contains the generated sequence transaction type and a UVM sequencer, which drives the transaction to the DUT.

  • The scoreboard directory contains the generated UVM scoreboard.

  • The uvm_artifacts directory contains UVM components, such as monitors, drivers, and agents, required for the UVM environment.

Run Generated UVM Test Bench

  1. Start Modelsim® or Questasim in GUI mode.

  2. In the HDL simulator, navigate to the top directory: cd hdlv_uvmbuild_uvmbuild\uvm_testbench\top\

  3. In the HDL simulator, enter this command to run your simulation: do run_tb_mq.do

Input Arguments

collapse all

Design under test subsystem, specified as a character vector or string scalar representing a DUT-subsystem name or full block path.

Example: 'hdlv_uvmbuild/DUT'

Data Types: char | string

Sequence subsystem, specified as a character vector or string scalar representing a sequence-subsystem name or full block path.

Example: 'hdlv_uvmbuild/sequence'

Data Types: char | string

Scoreboard subsystem, specified as a character vector or string scalar representing a scoreboard-subsystem name or full block path.

Example: 'hdlv_uvmbuild/scoreboard'

Data Types: char | string

Introduced in R2019b